LXR uboot/arch/arm/mach-tegra/xusb-padctl-common.h

   1/*
   2 * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
   3 *
   4 * SPDX-License-Identifier: GPL-2.0
   5 */
   6
   7#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
   8#define _TEGRA_XUSB_PADCTL_COMMON_H_
   9
  10#include <common.h>
  11#include <fdtdec.h>
  12#include <dm/ofnode.h>
  13
  14#include <asm/io.h>
  15#include <asm/arch-tegra/xusb-padctl.h>
  16#include <linux/ioport.h>
  17
  18struct tegra_xusb_padctl_lane {
  19        const char *name;
  20
  21        unsigned int offset;
  22        unsigned int shift;
  23        unsigned int mask;
  24        unsigned int iddq;
  25
  26        const unsigned int *funcs;
  27        unsigned int num_funcs;
  28};
  29
  30struct tegra_xusb_phy_ops {
  31        int (*prepare)(struct tegra_xusb_phy *phy);
  32        int (*enable)(struct tegra_xusb_phy *phy);
  33        int (*disable)(struct tegra_xusb_phy *phy);
  34        int (*unprepare)(struct tegra_xusb_phy *phy);
  35};
  36
  37struct tegra_xusb_phy {
  38        unsigned int type;
  39        const struct tegra_xusb_phy_ops *ops;
  40        struct tegra_xusb_padctl *padctl;
  41};
  42
  43struct tegra_xusb_padctl_pin {
  44        const struct tegra_xusb_padctl_lane *lane;
  45
  46        unsigned int func;
  47        int iddq;
  48};
  49
  50#define MAX_GROUPS 5
  51#define MAX_PINS 7
  52
  53struct tegra_xusb_padctl_group {
  54        const char *name;
  55
  56        const char *pins[MAX_PINS];
  57        unsigned int num_pins;
  58
  59        const char *func;
  60        int iddq;
  61};
  62
  63struct tegra_xusb_padctl_soc {
  64        const struct tegra_xusb_padctl_lane *lanes;
  65        unsigned int num_lanes;
  66        const char *const *functions;
  67        unsigned int num_functions;
  68        struct tegra_xusb_phy *phys;
  69        unsigned int num_phys;
  70};
  71
  72struct tegra_xusb_padctl_config {
  73        const char *name;
  74
  75        struct tegra_xusb_padctl_group groups[MAX_GROUPS];
  76        unsigned int num_groups;
  77};
  78
  79struct tegra_xusb_padctl {
  80        const struct tegra_xusb_padctl_soc *socdata;
  81        struct tegra_xusb_padctl_config config;
  82        struct resource regs;
  83        unsigned int enable;
  84
  85};
  86extern struct tegra_xusb_padctl padctl;
  87
  88static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
  89                               unsigned long offset)
  90{
  91        return readl(padctl->regs.start + offset);
  92}
  93
  94static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
  95                                 u32 value, unsigned long offset)
  96{
  97        writel(value, padctl->regs.start + offset);
  98}
  99
 100int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
 101                             const struct tegra_xusb_padctl_soc *socdata);
 102
 103#endif
 104