LXR uboot/arch/x86/lib/fsp/fsp

   1/*
   2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/fsp/fsp_support.h>
   9#include <asm/e820.h>
  10#include <asm/mrccache.h>
  11#include <asm/post.h>
  12
  13DECLARE_GLOBAL_DATA_PTR;
  14
  15int dram_init(void)
  16{
  17        phys_size_t ram_size = 0;
  18        const struct hob_header *hdr;
  19        struct hob_res_desc *res_desc;
  20
  21        hdr = gd->arch.hob_list;
  22        while (!end_of_hob(hdr)) {
  23                if (hdr->type == HOB_TYPE_RES_DESC) {
  24                        res_desc = (struct hob_res_desc *)hdr;
  25                        if (res_desc->type == RES_SYS_MEM ||
  26                            res_desc->type == RES_MEM_RESERVED) {
  27                                ram_size += res_desc->len;
  28                        }
  29                }
  30                hdr = get_next_hob(hdr);
  31        }
  32
  33        gd->ram_size = ram_size;
  34        post_code(POST_DRAM);
  35
  36#ifdef CONFIG_ENABLE_MRC_CACHE
  37        gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
  38                                               &gd->arch.mrc_output_len);
  39#endif
  40
  41        return 0;
  42}
  43
  44int dram_init_banksize(void)
  45{
  46        gd->bd->bi_dram[0].start = 0;
  47        gd->bd->bi_dram[0].size = gd->ram_size;
  48
  49        return 0;
  50}
  51
  52/*
  53 * This function looks for the highest region of memory lower than 4GB which
  54 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
  55 * It overrides the default implementation found elsewhere which simply
  56 * picks the end of ram, wherever that may be. The location of the stack,
  57 * the relocation address, and how far U-Boot is moved by relocation are
  58 * set in the global data structure.
  59 */
  60ulong board_get_usable_ram_top(ulong total_size)
  61{
  62        return fsp_get_usable_lowmem_top(gd->arch.hob_list);
  63}
  64
  65unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
  66{
  67        unsigned num_entries = 0;
  68        const struct hob_header *hdr;
  69        struct hob_res_desc *res_desc;
  70
  71        hdr = gd->arch.hob_list;
  72
  73        while (!end_of_hob(hdr)) {
  74                if (hdr->type == HOB_TYPE_RES_DESC) {
  75                        res_desc = (struct hob_res_desc *)hdr;
  76                        entries[num_entries].addr = res_desc->phys_start;
  77                        entries[num_entries].size = res_desc->len;
  78
  79                        if (res_desc->type == RES_SYS_MEM)
  80                                entries[num_entries].type = E820_RAM;
  81                        else if (res_desc->type == RES_MEM_RESERVED)
  82                                entries[num_entries].type = E820_RESERVED;
  83
  84                        num_entries++;
  85                }
  86                hdr = get_next_hob(hdr);
  87        }
  88
  89        /* Mark PCIe ECAM address range as reserved */
  90        entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
  91        entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
  92        entries[num_entries].type = E820_RESERVED;
  93        num_entries++;
  94
  95#ifdef CONFIG_HAVE_ACPI_RESUME
  96        /*
  97         * Everything between U-Boot's stack and ram top needs to be
  98         * reserved in order for ACPI S3 resume to work.
  99         */
 100        entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
 101        entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \
 102                CONFIG_STACK_SIZE;
 103        entries[num_entries].type = E820_RESERVED;
 104        num_entries++;
 105#endif
 106
 107        return num_entries;
 108}
 109