LXR uboot/board/freescale/mpc8315erdb/sdram.c

   1/*
   2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3 *
   4 * Authors: Nick.Spence@freescale.com
   5 *          Wilson.Lo@freescale.com
   6 *          scottwood@freescale.com
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#include <common.h>
  12#include <mpc83xx.h>
  13#include <spd_sdram.h>
  14
  15#include <asm/bitops.h>
  16#include <asm/io.h>
  17
  18#include <asm/processor.h>
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22static void resume_from_sleep(void)
  23{
  24        u32 magic = *(u32 *)0;
  25
  26        typedef void (*func_t)(void);
  27        func_t resume = *(func_t *)4;
  28
  29        if (magic == 0xf5153ae5)
  30                resume();
  31
  32        gd->flags &= ~GD_FLG_SILENT;
  33        puts("\nResume from sleep failed: bad magic word\n");
  34}
  35
  36/* Fixed sdram init -- doesn't use serial presence detect.
  37 *
  38 * This is useful for faster booting in configs where the RAM is unlikely
  39 * to be changed, or for things like NAND booting where space is tight.
  40 */
  41#ifndef CONFIG_SYS_RAMBOOT
  42static long fixed_sdram(void)
  43{
  44        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  45        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  46        u32 msize_log2 = __ilog2(msize);
  47
  48        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
  49        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  50        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  51
  52        /*
  53         * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  54         * or the DDR2 controller may fail to initialize correctly.
  55         */
  56        __udelay(50000);
  57
  58        im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
  59        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  60
  61        /* Currently we use only one CS, so disable the other bank. */
  62        im->ddr.cs_config[1] = 0;
  63
  64        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  65        im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  66        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  67        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  68        im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  69
  70        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  71                im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
  72        else
  73                im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  74
  75        im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  76        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  77        im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  78
  79        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  80        sync();
  81
  82        /* enable DDR controller */
  83        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  84        sync();
  85
  86        return msize;
  87}
  88#else
  89static long fixed_sdram(void)
  90{
  91        return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  92}
  93#endif /* CONFIG_SYS_RAMBOOT */
  94
  95int dram_init(void)
  96{
  97        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  98        u32 msize;
  99
 100        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 101                return -ENXIO;
 102
 103        /* DDR SDRAM */
 104        msize = fixed_sdram();
 105
 106        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 107                resume_from_sleep();
 108
 109        /* set total bus SDRAM size(bytes)  -- DDR */
 110        gd->ram_size = msize;
 111
 112        return 0;
 113}
 114