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6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/iomux-vf610.h>
11#include <asm/arch/ddrmc-vf610.h>
12#include <asm/arch/crm_regs.h>
13#include <asm/arch/clock.h>
14#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <miiphy.h>
17#include <netdev.h>
18#include <i2c.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22
23
24
25
26
27#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm
28#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \
29 PAD_CTL_INPUT_DIFFERENTIAL)
30#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \
31 PAD_CTL_PUS_100K_UP | \
32 PAD_CTL_INPUT_DIFFERENTIAL)
33
34enum {
35 PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
36 PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
37 PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
38 PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
39 PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
40 PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
41 PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
42 PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
43 PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
44 PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
45 PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
46 PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
47 PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
48 PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
49 PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
50 PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
51 PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
52 PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
53 PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
54 PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
55 PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
56 PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
57 PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
58 PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
59 PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
60 PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
61 PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
62 PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
63 PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
64 PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
65 PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
66 PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
67 PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
68 PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
69 PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
70 PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
71 PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
72 PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
73 PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
74 PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
75 PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
76 PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
77 PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
78 PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
79 PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
80 PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
81 PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
82 PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
83 PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
84 PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
85};
86
87static struct ddrmc_cr_setting pcm052_cr_settings[] = {
88
89 { 0x00002000, 105 },
90 { 0x00000020, 110 },
91
92 { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
93 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
94 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
95 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
96 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
97 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
98 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
99 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
100 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
101 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
102 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
103 { DDRMC_CR126_PHY_RDLAT(11), 126 },
104 { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
105 { DDRMC_CR137_PHYCTL_DL(2), 137 },
106 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
107 DDRMC_CR139_PHY_WRLV_DLL(3) |
108 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
109 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
110 DDRMC_CR154_PAD_ZQ_MODE(1) |
111 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
112 DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
113 { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
114 { DDRMC_CR158_TWR(6), 158 },
115 { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
116 DDRMC_CR161_TODTH_WR(6), 161 },
117
118 { 0, -1 }
119};
120
121
122
123#define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
124#define PCM052_DDRMC_PHY_CTRL 0x00290000
125#define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
126#define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
127
128static struct ddrmc_phy_setting pcm052_phy_settings[] = {
129 { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
130 { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
131 { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
132 { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
133 { DDRMC_PHY_DQS_TIMING, 1 },
134 { DDRMC_PHY_DQS_TIMING, 17 },
135 { DDRMC_PHY_DQS_TIMING, 33 },
136 { DDRMC_PHY_DQS_TIMING, 49 },
137 { PCM052_DDRMC_PHY_CTRL, 2 },
138 { PCM052_DDRMC_PHY_CTRL, 18 },
139 { PCM052_DDRMC_PHY_CTRL, 34 },
140 { DDRMC_PHY_MASTER_CTRL, 3 },
141 { DDRMC_PHY_MASTER_CTRL, 19 },
142 { DDRMC_PHY_MASTER_CTRL, 35 },
143 { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
144 { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
145 { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
146 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
147 { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
148
149
150 { 0, -1 }
151};
152
153int dram_init(void)
154{
155 static const iomux_v3_cfg_t pcm052_pads[] = {
156 PCM052_VF610_PAD_DDR_A15__DDR_A_15,
157 PCM052_VF610_PAD_DDR_A14__DDR_A_14,
158 PCM052_VF610_PAD_DDR_A13__DDR_A_13,
159 PCM052_VF610_PAD_DDR_A12__DDR_A_12,
160 PCM052_VF610_PAD_DDR_A11__DDR_A_11,
161 PCM052_VF610_PAD_DDR_A10__DDR_A_10,
162 PCM052_VF610_PAD_DDR_A9__DDR_A_9,
163 PCM052_VF610_PAD_DDR_A8__DDR_A_8,
164 PCM052_VF610_PAD_DDR_A7__DDR_A_7,
165 PCM052_VF610_PAD_DDR_A6__DDR_A_6,
166 PCM052_VF610_PAD_DDR_A5__DDR_A_5,
167 PCM052_VF610_PAD_DDR_A4__DDR_A_4,
168 PCM052_VF610_PAD_DDR_A3__DDR_A_3,
169 PCM052_VF610_PAD_DDR_A2__DDR_A_2,
170 PCM052_VF610_PAD_DDR_A1__DDR_A_1,
171 PCM052_VF610_PAD_DDR_A0__DDR_A_0,
172 PCM052_VF610_PAD_DDR_BA2__DDR_BA_2,
173 PCM052_VF610_PAD_DDR_BA1__DDR_BA_1,
174 PCM052_VF610_PAD_DDR_BA0__DDR_BA_0,
175 PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B,
176 PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0,
177 PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0,
178 PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0,
179 PCM052_VF610_PAD_DDR_D15__DDR_D_15,
180 PCM052_VF610_PAD_DDR_D14__DDR_D_14,
181 PCM052_VF610_PAD_DDR_D13__DDR_D_13,
182 PCM052_VF610_PAD_DDR_D12__DDR_D_12,
183 PCM052_VF610_PAD_DDR_D11__DDR_D_11,
184 PCM052_VF610_PAD_DDR_D10__DDR_D_10,
185 PCM052_VF610_PAD_DDR_D9__DDR_D_9,
186 PCM052_VF610_PAD_DDR_D8__DDR_D_8,
187 PCM052_VF610_PAD_DDR_D7__DDR_D_7,
188 PCM052_VF610_PAD_DDR_D6__DDR_D_6,
189 PCM052_VF610_PAD_DDR_D5__DDR_D_5,
190 PCM052_VF610_PAD_DDR_D4__DDR_D_4,
191 PCM052_VF610_PAD_DDR_D3__DDR_D_3,
192 PCM052_VF610_PAD_DDR_D2__DDR_D_2,
193 PCM052_VF610_PAD_DDR_D1__DDR_D_1,
194 PCM052_VF610_PAD_DDR_D0__DDR_D_0,
195 PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1,
196 PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0,
197 PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1,
198 PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0,
199 PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B,
200 PCM052_VF610_PAD_DDR_WE__DDR_WE_B,
201 PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0,
202 PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1,
203 PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
204 PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0,
205 PCM052_VF610_PAD_DDR_RESETB,
206 };
207
208#if defined(CONFIG_TARGET_PCM052)
209
210 static const struct ddr3_jedec_timings pcm052_ddr_timings = {
211 .tinit = 5,
212 .trst_pwron = 80000,
213 .cke_inactive = 200000,
214 .wrlat = 5,
215 .caslat_lin = 12,
216 .trc = 6,
217 .trrd = 4,
218 .tccd = 4,
219 .tbst_int_interval = 4,
220 .tfaw = 18,
221 .trp = 6,
222 .twtr = 4,
223 .tras_min = 15,
224 .tmrd = 4,
225 .trtp = 4,
226 .tras_max = 14040,
227 .tmod = 12,
228 .tckesr = 4,
229 .tcke = 3,
230 .trcd_int = 6,
231 .tras_lockout = 1,
232 .tdal = 10,
233 .bstlen = 3,
234 .tdll = 512,
235 .trp_ab = 6,
236 .tref = 1542,
237 .trfc = 64,
238 .tref_int = 5,
239 .tpdex = 3,
240 .txpdll = 10,
241 .txsnr = 68,
242 .txsr = 506,
243 .cksrx = 5,
244 .cksre = 5,
245 .freq_chg_en = 1,
246 .zqcl = 256,
247 .zqinit = 512,
248 .zqcs = 64,
249 .ref_per_zq = 64,
250 .zqcs_rotate = 1,
251 .aprebit = 10,
252 .cmd_age_cnt = 255,
253 .age_cnt = 255,
254 .q_fullness = 0,
255 .odt_rd_mapcs0 = 1,
256 .odt_wr_mapcs0 = 1,
257 .wlmrd = 40,
258 .wldqsen = 25,
259 };
260
261 const int row_diff = 2;
262
263#elif defined(CONFIG_TARGET_BK4R1)
264
265 static const struct ddr3_jedec_timings pcm052_ddr_timings = {
266 .tinit = 5,
267 .trst_pwron = 80000,
268 .cke_inactive = 200000,
269 .wrlat = 5,
270 .caslat_lin = 12,
271 .trc = 6,
272 .trrd = 4,
273 .tccd = 4,
274 .tbst_int_interval = 0,
275 .tfaw = 16,
276 .trp = 6,
277 .twtr = 4,
278 .tras_min = 15,
279 .tmrd = 4,
280 .trtp = 4,
281 .tras_max = 28080,
282 .tmod = 12,
283 .tckesr = 4,
284 .tcke = 3,
285 .trcd_int = 6,
286 .tras_lockout = 1,
287 .tdal = 12,
288 .bstlen = 3,
289 .tdll = 512,
290 .trp_ab = 6,
291 .tref = 3120,
292 .trfc = 104,
293 .tref_int = 0,
294 .tpdex = 3,
295 .txpdll = 10,
296 .txsnr = 108,
297 .txsr = 512,
298 .cksrx = 5,
299 .cksre = 5,
300 .freq_chg_en = 1,
301 .zqcl = 256,
302 .zqinit = 512,
303 .zqcs = 64,
304 .ref_per_zq = 64,
305 .zqcs_rotate = 1,
306 .aprebit = 10,
307 .cmd_age_cnt = 255,
308 .age_cnt = 255,
309 .q_fullness = 0,
310 .odt_rd_mapcs0 = 1,
311 .odt_wr_mapcs0 = 1,
312 .wlmrd = 40,
313 .wldqsen = 25,
314 };
315
316 const int row_diff = 1;
317
318#else
319
320#error DDR characteristics undefined for this target. Please define them.
321
322#endif
323
324 imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
325
326 ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
327 pcm052_phy_settings, 1, row_diff);
328
329 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
330
331 return 0;
332}
333
334static void setup_iomux_uart(void)
335{
336 static const iomux_v3_cfg_t uart1_pads[] = {
337 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL),
338 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL),
339 };
340
341 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
342}
343
344#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
345 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
346
347static void setup_iomux_enet(void)
348{
349 static const iomux_v3_cfg_t enet0_pads[] = {
350 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
351 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
352 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
353 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
354 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
355 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
356 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
357 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
358 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
359 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
360 };
361
362 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
363}
364
365
366
367
368
369static void setup_iomux_i2c(void)
370{
371 static const iomux_v3_cfg_t i2c_pads[] = {
372 VF610_PAD_PTA22__I2C2_SCL,
373 VF610_PAD_PTA23__I2C2_SDA,
374 };
375
376 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
377}
378
379#ifdef CONFIG_NAND_VF610_NFC
380static void setup_iomux_nfc(void)
381{
382 static const iomux_v3_cfg_t nfc_pads[] = {
383 VF610_PAD_PTD31__NF_IO15,
384 VF610_PAD_PTD30__NF_IO14,
385 VF610_PAD_PTD29__NF_IO13,
386 VF610_PAD_PTD28__NF_IO12,
387 VF610_PAD_PTD27__NF_IO11,
388 VF610_PAD_PTD26__NF_IO10,
389 VF610_PAD_PTD25__NF_IO9,
390 VF610_PAD_PTD24__NF_IO8,
391 VF610_PAD_PTD23__NF_IO7,
392 VF610_PAD_PTD22__NF_IO6,
393 VF610_PAD_PTD21__NF_IO5,
394 VF610_PAD_PTD20__NF_IO4,
395 VF610_PAD_PTD19__NF_IO3,
396 VF610_PAD_PTD18__NF_IO2,
397 VF610_PAD_PTD17__NF_IO1,
398 VF610_PAD_PTD16__NF_IO0,
399 VF610_PAD_PTB24__NF_WE_B,
400 VF610_PAD_PTB25__NF_CE0_B,
401 VF610_PAD_PTB27__NF_RE_B,
402 VF610_PAD_PTC26__NF_RB_B,
403 VF610_PAD_PTC27__NF_ALE,
404 VF610_PAD_PTC28__NF_CLE
405 };
406
407 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
408}
409#endif
410
411static void setup_iomux_qspi(void)
412{
413 static const iomux_v3_cfg_t qspi0_pads[] = {
414 VF610_PAD_PTD0__QSPI0_A_QSCK,
415 VF610_PAD_PTD1__QSPI0_A_CS0,
416 VF610_PAD_PTD2__QSPI0_A_DATA3,
417 VF610_PAD_PTD3__QSPI0_A_DATA2,
418 VF610_PAD_PTD4__QSPI0_A_DATA1,
419 VF610_PAD_PTD5__QSPI0_A_DATA0,
420 VF610_PAD_PTD7__QSPI0_B_QSCK,
421 VF610_PAD_PTD8__QSPI0_B_CS0,
422 VF610_PAD_PTD9__QSPI0_B_DATA3,
423 VF610_PAD_PTD10__QSPI0_B_DATA2,
424 VF610_PAD_PTD11__QSPI0_B_DATA1,
425 VF610_PAD_PTD12__QSPI0_B_DATA0,
426 };
427
428 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
429}
430
431#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
432 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
433
434struct fsl_esdhc_cfg esdhc_cfg[1] = {
435 {ESDHC1_BASE_ADDR},
436};
437
438int board_mmc_getcd(struct mmc *mmc)
439{
440
441 return 1;
442}
443
444int board_mmc_init(bd_t *bis)
445{
446 static const iomux_v3_cfg_t esdhc1_pads[] = {
447 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
448 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
449 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
450 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
451 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
452 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
453 };
454
455 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
456
457 imx_iomux_v3_setup_multiple_pads(
458 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
459
460 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
461}
462
463static void clock_init(void)
464{
465 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
466 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
467
468 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
469 CCM_CCGR0_UART1_CTRL_MASK);
470 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
471 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
472 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
473 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
474 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
475 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
476 CCM_CCGR2_QSPI0_CTRL_MASK);
477 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
478 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
479 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
480 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
481 CCM_CCGR4_GPC_CTRL_MASK);
482 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
483 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
484 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
485 CCM_CCGR7_SDHC1_CTRL_MASK);
486 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
487 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
488 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
489 CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK);
490
491 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
492 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
493 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
494 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
495
496 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
497 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
498 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
499 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
500 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
501 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
502 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
503 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
504 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
505 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
506 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
507 CCM_CACRR_ARM_CLK_DIV(0));
508 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
509 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
510 CCM_CSCMR1_QSPI0_CLK_SEL(3) |
511 CCM_CSCMR1_NFC_CLK_SEL(0));
512 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
513 CCM_CSCDR1_RMII_CLK_EN);
514 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
515 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
516 CCM_CSCDR2_NFC_EN);
517 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
518 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
519 CCM_CSCDR3_QSPI0_X2_DIV(1) |
520 CCM_CSCDR3_QSPI0_X4_DIV(3) |
521 CCM_CSCDR3_NFC_PRE_DIV(5));
522 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
523 CCM_CSCMR2_RMII_CLK_SEL(0));
524}
525
526static void mscm_init(void)
527{
528 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
529 int i;
530
531 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
532 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
533}
534
535int board_phy_config(struct phy_device *phydev)
536{
537 if (phydev->drv->config)
538 phydev->drv->config(phydev);
539
540 return 0;
541}
542
543int board_early_init_f(void)
544{
545 clock_init();
546 mscm_init();
547 setup_iomux_uart();
548 setup_iomux_enet();
549 setup_iomux_i2c();
550 setup_iomux_qspi();
551 setup_iomux_nfc();
552
553 return 0;
554}
555
556int board_init(void)
557{
558 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
559
560
561 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
562
563
564
565
566
567
568
569
570 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
571
572 return 0;
573}
574
575int checkboard(void)
576{
577 puts("Board: PCM-052\n");
578
579 return 0;
580}
581
582static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
583 char * const argv[])
584{
585 ulong addr;
586
587
588 argc--; argv++;
589
590
591
592
593
594 if (argc)
595 addr = simple_strtoul(argv[0], NULL, 16);
596 else
597 addr = load_addr;
598
599
600
601
602 writel(addr + 0x401, 0x4006E028);
603
604
605
606
607 writel(0x15a5a, 0x4006B08C);
608
609 return 1;
610}
611
612U_BOOT_CMD(
613 m4go, 2 , 1 , do_m4go,
614 "start the secondary Cortex-M4 from scatter file image",
615 "[<addr>]\n"
616 " - start secondary Cortex-M4 core using a scatter file image\n"
617 "The argument needs to be a scatter file\n"
618);
619
