uboot/board/ti/am3517crane/am3517crane.h
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   1/*
   2 * am3517crane.h - Header file for the AM3517 CraneBoard.
   3 *
   4 * Author: Srinath R <srinath@mistralsolutions.com>
   5 *
   6 * Based on logicpd/am3517evm/am3517evm.h
   7 *
   8 * Copyright (C) 2011 Mistral Solutions Pvt Ltd
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 */
  12
  13#ifndef _AM3517CRANE_H_
  14#define _AM3517CRANE_H_
  15
  16const omap3_sysinfo sysinfo = {
  17        DDR_DISCRETE,
  18        "CraneBoard",
  19        "NAND",
  20};
  21
  22/*
  23 * IEN  - Input Enable
  24 * IDIS - Input Disable
  25 * PTD  - Pull type Down
  26 * PTU  - Pull type Up
  27 * DIS  - Pull type selection is inactive
  28 * EN   - Pull type selection is active
  29 * M0   - Mode 0
  30 * The commented string gives the final mux configuration for that pin
  31 */
  32#define MUX_AM3517CRANE()\
  33        /*SDRC*/\
  34        MUX_VAL(CP(SDRC_D0),    (IEN  | PTD | DIS | M0))\
  35        MUX_VAL(CP(SDRC_D1),    (IEN  | PTD | DIS | M0))\
  36        MUX_VAL(CP(SDRC_D2),    (IEN  | PTD | DIS | M0))\
  37        MUX_VAL(CP(SDRC_D3),    (IEN  | PTD | DIS | M0))\
  38        MUX_VAL(CP(SDRC_D4),    (IEN  | PTD | DIS | M0))\
  39        MUX_VAL(CP(SDRC_D5),    (IEN  | PTD | DIS | M0))\
  40        MUX_VAL(CP(SDRC_D6),    (IEN  | PTD | DIS | M0))\
  41        MUX_VAL(CP(SDRC_D7),    (IEN  | PTD | DIS | M0))\
  42        MUX_VAL(CP(SDRC_D8),    (IEN  | PTD | DIS | M0))\
  43        MUX_VAL(CP(SDRC_D9),    (IEN  | PTD | DIS | M0))\
  44        MUX_VAL(CP(SDRC_D10),   (IEN  | PTD | DIS | M0))\
  45        MUX_VAL(CP(SDRC_D11),   (IEN  | PTD | DIS | M0))\
  46        MUX_VAL(CP(SDRC_D12),   (IEN  | PTD | DIS | M0))\
  47        MUX_VAL(CP(SDRC_D13),   (IEN  | PTD | DIS | M0))\
  48        MUX_VAL(CP(SDRC_D14),   (IEN  | PTD | DIS | M0))\
  49        MUX_VAL(CP(SDRC_D15),   (IEN  | PTD | DIS | M0))\
  50        MUX_VAL(CP(SDRC_D16),   (IEN  | PTD | DIS | M0))\
  51        MUX_VAL(CP(SDRC_D17),   (IEN  | PTD | DIS | M0))\
  52        MUX_VAL(CP(SDRC_D18),   (IEN  | PTD | DIS | M0))\
  53        MUX_VAL(CP(SDRC_D19),   (IEN  | PTD | DIS | M0))\
  54        MUX_VAL(CP(SDRC_D20),   (IEN  | PTD | DIS | M0))\
  55        MUX_VAL(CP(SDRC_D21),   (IEN  | PTD | DIS | M0))\
  56        MUX_VAL(CP(SDRC_D22),   (IEN  | PTD | DIS | M0))\
  57        MUX_VAL(CP(SDRC_D23),   (IEN  | PTD | DIS | M0))\
  58        MUX_VAL(CP(SDRC_D24),   (IEN  | PTD | DIS | M0))\
  59        MUX_VAL(CP(SDRC_D25),   (IEN  | PTD | DIS | M0))\
  60        MUX_VAL(CP(SDRC_D26),   (IEN  | PTD | DIS | M0))\
  61        MUX_VAL(CP(SDRC_D27),   (IEN  | PTD | DIS | M0))\
  62        MUX_VAL(CP(SDRC_D28),   (IEN  | PTD | DIS | M0))\
  63        MUX_VAL(CP(SDRC_D29),   (IEN  | PTD | DIS | M0))\
  64        MUX_VAL(CP(SDRC_D30),   (IEN  | PTD | DIS | M0))\
  65        MUX_VAL(CP(SDRC_D31),   (IEN  | PTD | DIS | M0))\
  66        MUX_VAL(CP(SDRC_CLK),   (IEN  | PTD | DIS | M0))\
  67        MUX_VAL(CP(SDRC_DQS0),  (IEN  | PTD | DIS | M0))\
  68        MUX_VAL(CP(SDRC_CKE0),  (M0))\
  69        MUX_VAL(CP(SDRC_DQS1),  (IEN  | PTD | DIS | M0))\
  70        MUX_VAL(CP(SDRC_DQS2),  (IEN  | PTD | DIS | M0))\
  71        MUX_VAL(CP(SDRC_DQS3),  (IEN  | PTD | DIS | M0))\
  72        MUX_VAL(CP(SDRC_DQS0N), (IEN  | PTD | EN  | M0))\
  73        MUX_VAL(CP(SDRC_DQS1N), (IEN  | PTD | EN  | M0))\
  74        MUX_VAL(CP(SDRC_DQS2N), (IEN  | PTD | EN  | M0))\
  75        MUX_VAL(CP(SDRC_DQS3N), (IEN  | PTD | EN  | M0))\
  76        MUX_VAL(CP(SDRC_CKE0),  (M0))\
  77        MUX_VAL(CP(SDRC_CKE1),  (M0))\
  78        /*sdrc_strben_dly0*/\
  79        MUX_VAL(CP(STRBEN_DLY0),    (IEN  | PTD | EN  | M0))\
  80        /*sdrc_strben_dly1*/\
  81        MUX_VAL(CP(STRBEN_DLY1),        (IEN  | PTD | EN  | M0))\
  82        /*GPMC*/\
  83        MUX_VAL(CP(GPMC_A1),    (M7))\
  84        MUX_VAL(CP(GPMC_A2),    (IDIS | PTU | DIS | M4))\
  85        MUX_VAL(CP(GPMC_A3),    (IDIS | PTU | EN  | M4))\
  86        MUX_VAL(CP(GPMC_A4),    (IDIS | PTU | EN  | M4))\
  87        MUX_VAL(CP(GPMC_A5),    (IDIS | PTU | EN  | M4))\
  88        MUX_VAL(CP(GPMC_A6),    (M7))\
  89        MUX_VAL(CP(GPMC_A7),    (IDIS | PTU | EN  | M4))\
  90        MUX_VAL(CP(GPMC_A8),    (IEN  | PTU | EN  | M4))\
  91        MUX_VAL(CP(GPMC_A9),    (M7))\
  92        MUX_VAL(CP(GPMC_A10),   (M7))\
  93        MUX_VAL(CP(GPMC_D0),    (IEN  | PTU | EN  | M0))\
  94        MUX_VAL(CP(GPMC_D1),    (IEN  | PTU | EN  | M0))\
  95        MUX_VAL(CP(GPMC_D2),    (IEN  | PTU | EN  | M0))\
  96        MUX_VAL(CP(GPMC_D3),    (IEN  | PTU | EN  | M0))\
  97        MUX_VAL(CP(GPMC_D4),    (IEN  | PTU | EN  | M0))\
  98        MUX_VAL(CP(GPMC_D5),    (IEN  | PTU | EN  | M0))\
  99        MUX_VAL(CP(GPMC_D6),    (IEN  | PTU | EN  | M0))\
 100        MUX_VAL(CP(GPMC_D7),    (IEN  | PTU | EN  | M0))\
 101        MUX_VAL(CP(GPMC_D8),    (IEN  | PTU | EN  | M0))\
 102        MUX_VAL(CP(GPMC_D9),    (IEN  | PTU | EN  | M0))\
 103        MUX_VAL(CP(GPMC_D10),   (IEN  | PTU | EN  | M0))\
 104        MUX_VAL(CP(GPMC_D11),   (IEN  | PTU | EN  | M0))\
 105        MUX_VAL(CP(GPMC_D12),   (IEN  | PTU | EN  | M0))\
 106        MUX_VAL(CP(GPMC_D13),   (IEN  | PTU | EN  | M0))\
 107        MUX_VAL(CP(GPMC_D14),   (IEN  | PTU | EN  | M0))\
 108        MUX_VAL(CP(GPMC_D15),   (IEN  | PTU | EN  | M0))\
 109        MUX_VAL(CP(GPMC_NCS0),  (IDIS | PTU | EN  | M0))\
 110        MUX_VAL(CP(GPMC_NCS1),  (IDIS | PTU | EN  | M4))\
 111        MUX_VAL(CP(GPMC_NCS2),  (M7))\
 112        MUX_VAL(CP(GPMC_NCS3),  (M7))\
 113        MUX_VAL(CP(GPMC_NCS4),  (M7))\
 114        MUX_VAL(CP(GPMC_NCS5),  (M7))\
 115        MUX_VAL(CP(GPMC_NCS6),  (M7))\
 116        MUX_VAL(CP(GPMC_NCS7),  (M7))\
 117        MUX_VAL(CP(GPMC_CLK),   (IDIS | PTU | EN  | M0))/*TP*/\
 118        MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0))\
 119        MUX_VAL(CP(GPMC_NOE),   (IDIS | PTD | DIS | M0))\
 120        MUX_VAL(CP(GPMC_NWE),   (IDIS | PTD | DIS | M0))\
 121        MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0))\
 122        MUX_VAL(CP(GPMC_NBE1),  (M7))\
 123        MUX_VAL(CP(GPMC_NWP),   (IEN  | PTD | DIS | M0))\
 124        MUX_VAL(CP(GPMC_WAIT0), (IEN  | PTD | DIS | M0))\
 125        MUX_VAL(CP(GPMC_WAIT1), (M7))\
 126        MUX_VAL(CP(GPMC_WAIT2), (M7))\
 127        MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN  | M4))/*GPIO_65*/\
 128        /*DSS*/\
 129        MUX_VAL(CP(DSS_PCLK),   (IDIS | PTD | DIS | M0))\
 130        MUX_VAL(CP(DSS_HSYNC),  (IDIS | PTD | DIS | M0))\
 131        MUX_VAL(CP(DSS_VSYNC),  (IDIS | PTD | DIS | M0))\
 132        MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\
 133        MUX_VAL(CP(DSS_DATA0),  (IDIS | PTD | DIS | M0))\
 134        MUX_VAL(CP(DSS_DATA1),  (IDIS | PTD | DIS | M0))\
 135        MUX_VAL(CP(DSS_DATA2),  (IDIS | PTD | DIS | M0))\
 136        MUX_VAL(CP(DSS_DATA3),  (IDIS | PTD | DIS | M0))\
 137        MUX_VAL(CP(DSS_DATA4),  (IDIS | PTD | DIS | M0))\
 138        MUX_VAL(CP(DSS_DATA5),  (IDIS | PTD | DIS | M0))\
 139        MUX_VAL(CP(DSS_DATA6),  (IDIS | PTD | DIS | M0))\
 140        MUX_VAL(CP(DSS_DATA7),  (IDIS | PTD | DIS | M0))\
 141        MUX_VAL(CP(DSS_DATA8),  (IDIS | PTD | DIS | M0))\
 142        MUX_VAL(CP(DSS_DATA9),  (IDIS | PTD | DIS | M0))\
 143        MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\
 144        MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\
 145        MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\
 146        MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\
 147        MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\
 148        MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
 149        MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\
 150        MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\
 151        MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\
 152        MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\
 153        MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\
 154        MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\
 155        MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\
 156        MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\
 157        /*MMC1*/\
 158        MUX_VAL(CP(MMC1_CLK),   (IEN  | PTU | EN  | M0))\
 159        MUX_VAL(CP(MMC1_CMD),   (IEN  | PTU | DIS | M0))\
 160        MUX_VAL(CP(MMC1_DAT0),  (IEN  | PTU | DIS | M0))\
 161        MUX_VAL(CP(MMC1_DAT1),  (IEN  | PTU | DIS | M0))\
 162        MUX_VAL(CP(MMC1_DAT2),  (IEN  | PTU | DIS | M0))\
 163        MUX_VAL(CP(MMC1_DAT3),  (IEN  | PTU | DIS | M0))\
 164        MUX_VAL(CP(MMC1_DAT4),  (IEN  | PTU | DIS | M0))\
 165        MUX_VAL(CP(MMC1_DAT5),  (IEN  | PTU | DIS | M0))\
 166        MUX_VAL(CP(MMC1_DAT6),  (IEN  | PTU | DIS | M0))\
 167        MUX_VAL(CP(MMC1_DAT7),  (IEN  | PTU | DIS | M0))\
 168        /*MMC2*/\
 169        MUX_VAL(CP(MMC2_CLK),   (IEN  | PTD | EN  | M0))\
 170        MUX_VAL(CP(MMC2_CMD),   (IEN  | PTD | DIS | M0))\
 171        MUX_VAL(CP(MMC2_DAT0),  (IEN  | PTD | DIS | M0))\
 172        MUX_VAL(CP(MMC2_DAT1),  (IEN  | PTD | DIS | M0))\
 173        MUX_VAL(CP(MMC2_DAT2),  (IEN  | PTD | DIS | M0))\
 174        MUX_VAL(CP(MMC2_DAT3),  (IEN  | PTD | DIS | M0))\
 175        MUX_VAL(CP(MMC2_DAT4),  (IEN  | PTD | DIS | M0))\
 176        MUX_VAL(CP(MMC2_DAT5),  (IEN  | PTD | DIS | M0))\
 177        MUX_VAL(CP(MMC2_DAT6),  (IEN  | PTD | DIS | M0))\
 178        MUX_VAL(CP(MMC2_DAT7),  (IEN  | PTD | DIS | M0))\
 179        /*McBSP*/\
 180        MUX_VAL(CP(MCBSP_CLKS), (IEN  | PTU | DIS | M0))\
 181        MUX_VAL(CP(MCBSP1_CLKR),        (IEN  | PTD | DIS | M0))\
 182        MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN  | M0))\
 183        MUX_VAL(CP(MCBSP1_DX),  (IDIS | PTD | DIS | M0))\
 184        MUX_VAL(CP(MCBSP1_DR),  (IEN  | PTD | DIS | M0))\
 185        MUX_VAL(CP(MCBSP1_FSX), (IEN  | PTD | DIS | M0))\
 186        MUX_VAL(CP(MCBSP1_CLKX),        (IEN  | PTD | DIS | M0))\
 187        \
 188        MUX_VAL(CP(MCBSP2_FSX), (M7))\
 189        MUX_VAL(CP(MCBSP2_CLKX),        (M7))\
 190        MUX_VAL(CP(MCBSP2_DR),  (M7))\
 191        MUX_VAL(CP(MCBSP2_DX),  (M7))\
 192        \
 193        MUX_VAL(CP(MCBSP3_DX),  (IDIS | PTD | DIS | M0))\
 194        MUX_VAL(CP(MCBSP3_DR),  (IEN  | PTD | DIS | M0))\
 195        MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M0))\
 196        MUX_VAL(CP(MCBSP3_FSX), (IEN  | PTD | DIS | M0))\
 197        \
 198        MUX_VAL(CP(MCBSP4_CLKX),        (M7))\
 199        MUX_VAL(CP(MCBSP4_DR),  (M7))\
 200        MUX_VAL(CP(MCBSP4_DX),  (M7))\
 201        MUX_VAL(CP(MCBSP4_FSX), (M7))\
 202        /*UART*/\
 203        MUX_VAL(CP(UART1_TX),   (M7))\
 204        MUX_VAL(CP(UART1_RTS),  (M7))\
 205        MUX_VAL(CP(UART1_CTS),  (M7))\
 206        MUX_VAL(CP(UART1_RX),   (M7))\
 207        \
 208        MUX_VAL(CP(UART2_CTS),  (M7))\
 209        MUX_VAL(CP(UART2_RTS),  (M7))\
 210        MUX_VAL(CP(UART2_TX),   (M7))\
 211        MUX_VAL(CP(UART2_RX),   (M7))\
 212        \
 213        MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTU | DIS | M0))\
 214        MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0))\
 215        MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0))\
 216        MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0))\
 217        /*I2C 1, 2, 3*/\
 218        MUX_VAL(CP(I2C1_SCL),   (IEN  | PTU | EN  | M0))\
 219        MUX_VAL(CP(I2C1_SDA),   (IEN  | PTU | EN  | M0))\
 220        MUX_VAL(CP(I2C2_SCL),   (IEN  | PTU | EN  | M0))\
 221        MUX_VAL(CP(I2C2_SDA),   (IEN  | PTU | EN  | M0))\
 222        MUX_VAL(CP(I2C3_SCL),   (IEN  | PTU | EN  | M0))\
 223        MUX_VAL(CP(I2C3_SDA),   (IEN  | PTU | EN  | M0))\
 224        /*McSPI*/\
 225        MUX_VAL(CP(MCSPI1_CLK), (IEN  | PTU | EN  | M4))/*GPIO_171 TP*/\
 226        MUX_VAL(CP(MCSPI1_SIMO),    (IEN  | PTU | EN  | M4))/*GPIO_172 TP*/\
 227        MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTU | EN  | M4))/*GPIO_173 TP*/\
 228        MUX_VAL(CP(MCSPI1_CS0), (IEN  | PTU | EN  | M4))/*GPIO_174 TP*/\
 229        MUX_VAL(CP(MCSPI1_CS1), (IEN  | PTU | EN  | M4))/*GPIO_175 TP*/\
 230        MUX_VAL(CP(MCSPI1_CS2), (IEN  | PTU | EN  | M4))/*GPIO_176 TP*/\
 231        MUX_VAL(CP(MCSPI1_CS3), (IEN  | PTD | EN  | M4))/*GPIO_176 TP*/\
 232        \
 233        MUX_VAL(CP(MCSPI2_CLK), (M7))\
 234        MUX_VAL(CP(MCSPI2_SIMO),    (M7))\
 235        MUX_VAL(CP(MCSPI2_SOMI),        (M7))\
 236        MUX_VAL(CP(MCSPI2_CS0), (M7))\
 237        MUX_VAL(CP(MCSPI2_CS1), (M7))\
 238        /*CCDC*/\
 239        MUX_VAL(CP(CCDC_PCLK),  (IEN  | PTU | EN  | M0))\
 240        MUX_VAL(CP(CCDC_FIELD), (IEN  | PTD | DIS | M1))/*CCDC_DATA8*/\
 241        MUX_VAL(CP(CCDC_HD),    (IEN  | PTU | EN  | M0))\
 242        MUX_VAL(CP(CCDC_VD),    (IEN  | PTU | EN  | M0))\
 243        MUX_VAL(CP(CCDC_WEN),   (IEN  | PTD | DIS | M1))/*CCDC_DATA9 */\
 244        MUX_VAL(CP(CCDC_DATA0), (IEN  | PTD | DIS | M0))\
 245        MUX_VAL(CP(CCDC_DATA1), (IEN  | PTD | DIS | M0))\
 246        MUX_VAL(CP(CCDC_DATA2), (IEN  | PTD | DIS | M0))\
 247        MUX_VAL(CP(CCDC_DATA3), (IEN  | PTD | DIS | M0))\
 248        MUX_VAL(CP(CCDC_DATA4), (IEN  | PTD | DIS | M0))\
 249        MUX_VAL(CP(CCDC_DATA5), (IEN  | PTD | DIS | M0))\
 250        MUX_VAL(CP(CCDC_DATA6), (IEN  | PTD | DIS | M0))\
 251        MUX_VAL(CP(CCDC_DATA7), (IEN  | PTD | DIS | M0))\
 252        /*RMII*/\
 253        MUX_VAL(CP(RMII_MDIO_DATA),     (IEN  |  M0))\
 254        MUX_VAL(CP(RMII_MDIO_CLK),      (M0))\
 255        MUX_VAL(CP(RMII_RXD0),  (IEN  | PTD | M0))\
 256        MUX_VAL(CP(RMII_RXD1),  (IEN  | PTD | M0))\
 257        MUX_VAL(CP(RMII_CRS_DV),        (IEN  | PTD | M0))\
 258        MUX_VAL(CP(RMII_RXER),  (PTD  | M0))\
 259        MUX_VAL(CP(RMII_TXD0),  (PTD  | M0))\
 260        MUX_VAL(CP(RMII_TXD1),  (PTD  | M0))\
 261        MUX_VAL(CP(RMII_TXEN),  (PTD  | M0))\
 262        MUX_VAL(CP(RMII_50MHZ_CLK),     (IEN  | PTD | EN  | M0))\
 263        /*HECC*/\
 264        MUX_VAL(CP(HECC1_TXD),  (IEN  | PTU | EN  | M0))\
 265        MUX_VAL(CP(HECC1_RXD),  (IEN  | PTU | EN  | M0))\
 266        /*HSUSB*/\
 267        MUX_VAL(CP(USB0_DRVBUS),        (IEN  | PTD | EN  | M0))\
 268        /*HDQ*/\
 269        MUX_VAL(CP(HDQ_SIO),    (IEN  | PTU | EN  | M4))\
 270        /*Control and debug*/\
 271        MUX_VAL(CP(SYS_32K),    (IEN  | PTD | DIS | M0))\
 272        MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\
 273        MUX_VAL(CP(SYS_NIRQ),   (IEN  | PTU | EN  | M0))\
 274        /*SYS_nRESWARM*/\
 275        MUX_VAL(CP(SYS_NRESWARM),       (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\
 276        MUX_VAL(CP(SYS_BOOT1),  (IEN  | PTD | DIS | M0))\
 277        MUX_VAL(CP(SYS_BOOT2),  (IEN  | PTD | DIS | M0))\
 278        MUX_VAL(CP(SYS_BOOT3),  (IEN  | PTD | DIS | M0))\
 279        MUX_VAL(CP(SYS_BOOT4),  (IEN  | PTD | DIS | M0))\
 280        MUX_VAL(CP(SYS_BOOT5),  (IEN  | PTD | DIS | M0))\
 281        MUX_VAL(CP(SYS_BOOT6),  (IDIS | PTD | DIS | M0))\
 282        MUX_VAL(CP(SYS_BOOT7),  (IEN  | PTD | EN  | M0))\
 283        MUX_VAL(CP(SYS_BOOT8),  (IEN  | PTD | EN  | M0))\
 284        MUX_VAL(CP(SYS_CLKOUT1),    (IEN  | PTD | DIS | M4))/*GPIO_10 TP*/\
 285        MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M0))\
 286        /*JTAG*/\
 287        MUX_VAL(CP(JTAG_NTRST), (IEN  | PTD | DIS | M0))\
 288        MUX_VAL(CP(JTAG_TCK),   (IEN  | PTD | DIS | M0))\
 289        MUX_VAL(CP(JTAG_TMS),   (IEN  | PTD | DIS | M0))\
 290        MUX_VAL(CP(JTAG_TDI),   (IEN  | PTD | DIS | M0))\
 291        MUX_VAL(CP(JTAG_EMU0),  (IEN  | PTD | DIS | M0))\
 292        MUX_VAL(CP(JTAG_EMU1),  (IEN  | PTD | DIS | M0))\
 293        /*ETK (ES2 onwards)*/\
 294        MUX_VAL(CP(ETK_CLK_ES2),    (IEN  | PTU | EN  | M3))\
 295        MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | DIS | M3))\
 296        MUX_VAL(CP(ETK_D0_ES2), (IEN  | PTD | DIS | M3))\
 297        MUX_VAL(CP(ETK_D1_ES2), (IEN  | PTD | DIS | M3))\
 298        MUX_VAL(CP(ETK_D2_ES2), (IEN  | PTD | EN  | M3))\
 299        MUX_VAL(CP(ETK_D3_ES2), (IEN  | PTD | DIS | M3))\
 300        MUX_VAL(CP(ETK_D4_ES2), (IEN  | PTD | DIS | M3))\
 301        MUX_VAL(CP(ETK_D5_ES2), (IEN  | PTD | DIS | M3))\
 302        MUX_VAL(CP(ETK_D6_ES2), (IEN  | PTD | DIS | M3))\
 303        MUX_VAL(CP(ETK_D7_ES2), (IEN  | PTD | DIS | M3))\
 304        MUX_VAL(CP(ETK_D8_ES2), (IEN  | PTD | DIS | M3))\
 305        MUX_VAL(CP(ETK_D9_ES2), (IEN  | PTD | DIS | M3))\
 306        MUX_VAL(CP(ETK_D10_ES2),    (M7))\
 307        MUX_VAL(CP(ETK_D11_ES2),    (M7))\
 308        MUX_VAL(CP(ETK_D12_ES2),    (M7))\
 309        MUX_VAL(CP(ETK_D13_ES2),    (M7))\
 310        MUX_VAL(CP(ETK_D14_ES2),    (M7))\
 311        MUX_VAL(CP(ETK_D15_ES2),        (M7))\
 312        /*Die to Die*/\
 313        MUX_VAL(CP(D2D_MCAD34), (IEN  | PTD | EN  | M0))\
 314        MUX_VAL(CP(D2D_MCAD35), (IEN  | PTD | EN  | M0))\
 315        MUX_VAL(CP(D2D_MCAD36), (IEN  | PTD | EN  | M0))\
 316        MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0))\
 317        MUX_VAL(CP(D2D_NRESPWRON),  (IEN  | PTD | EN  | M0))\
 318        MUX_VAL(CP(D2D_NRESWARM),   (IEN  | PTU | EN  | M0))\
 319        MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0))\
 320        MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0))\
 321        MUX_VAL(CP(D2D_SPINT),  (IEN  | PTD | EN  | M0))\
 322        MUX_VAL(CP(D2D_FRINT),  (IEN  | PTD | EN  | M0))\
 323        MUX_VAL(CP(D2D_DMAREQ0),    (IEN  | PTD | DIS | M0))\
 324        MUX_VAL(CP(D2D_DMAREQ1),    (IEN  | PTD | DIS | M0))\
 325        MUX_VAL(CP(D2D_DMAREQ2),    (IEN  | PTD | DIS | M0))\
 326        MUX_VAL(CP(D2D_DMAREQ3),    (IEN  | PTD | DIS | M0))\
 327        MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0))\
 328        MUX_VAL(CP(D2D_N3GTDI), (IEN  | PTD | DIS | M0))\
 329        MUX_VAL(CP(D2D_N3GTDO), (IEN  | PTD | DIS | M0))\
 330        MUX_VAL(CP(D2D_N3GTMS), (IEN  | PTD | DIS | M0))\
 331        MUX_VAL(CP(D2D_N3GTCK), (IEN  | PTD | DIS | M0))\
 332        MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0))\
 333        MUX_VAL(CP(D2D_MSTDBY), (IEN  | PTU | EN  | M0))\
 334        MUX_VAL(CP(D2D_SWAKEUP),    (IEN  | PTD | EN  | M0))\
 335        MUX_VAL(CP(D2D_IDLEREQ),    (IEN  | PTD | DIS | M0))\
 336        MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0))\
 337        MUX_VAL(CP(D2D_MWRITE), (IEN  | PTD | DIS | M0))\
 338        MUX_VAL(CP(D2D_SWRITE), (IEN  | PTD | DIS | M0))\
 339        MUX_VAL(CP(D2D_MREAD),  (IEN  | PTD | DIS | M0))\
 340        MUX_VAL(CP(D2D_SREAD),  (IEN  | PTD | DIS | M0))\
 341        MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0))\
 342        MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0))\
 343
 344#endif /* _AM3517CRANE_H_ */
 345
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.