uboot/drivers/mmc/sdhci.c
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   1/*
   2 * Copyright 2011, Marvell Semiconductor Inc.
   3 * Lei Wen <leiwen@marvell.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 *
   7 * Back ported to the 8xx platform (from the 8260 platform) by
   8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   9 */
  10
  11#include <common.h>
  12#include <errno.h>
  13#include <malloc.h>
  14#include <mmc.h>
  15#include <sdhci.h>
  16#include <wait_bit.h>
  17
  18#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  19void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  20#else
  21void *aligned_buffer;
  22#endif
  23
  24static void sdhci_reset(struct sdhci_host *host, u8 mask)
  25{
  26        unsigned long timeout;
  27
  28        /* Wait max 100 ms */
  29        timeout = 100;
  30        sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  31        while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  32                if (timeout == 0) {
  33                        printf("%s: Reset 0x%x never completed.\n",
  34                               __func__, (int)mask);
  35                        return;
  36                }
  37                timeout--;
  38                udelay(1000);
  39        }
  40}
  41
  42static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  43{
  44        int i;
  45        if (cmd->resp_type & MMC_RSP_136) {
  46                /* CRC is stripped so we need to do some shifting. */
  47                for (i = 0; i < 4; i++) {
  48                        cmd->response[i] = sdhci_readl(host,
  49                                        SDHCI_RESPONSE + (3-i)*4) << 8;
  50                        if (i != 3)
  51                                cmd->response[i] |= sdhci_readb(host,
  52                                                SDHCI_RESPONSE + (3-i)*4-1);
  53                }
  54        } else {
  55                cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  56        }
  57}
  58
  59static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  60{
  61        int i;
  62        char *offs;
  63        for (i = 0; i < data->blocksize; i += 4) {
  64                offs = data->dest + i;
  65                if (data->flags == MMC_DATA_READ)
  66                        *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  67                else
  68                        sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  69        }
  70}
  71
  72static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  73                                unsigned int start_addr)
  74{
  75        unsigned int stat, rdy, mask, timeout, block = 0;
  76        bool transfer_done = false;
  77#ifdef CONFIG_MMC_SDHCI_SDMA
  78        unsigned char ctrl;
  79        ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  80        ctrl &= ~SDHCI_CTRL_DMA_MASK;
  81        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  82#endif
  83
  84        timeout = 1000000;
  85        rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  86        mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  87        do {
  88                stat = sdhci_readl(host, SDHCI_INT_STATUS);
  89                if (stat & SDHCI_INT_ERROR) {
  90                        printf("%s: Error detected in status(0x%X)!\n",
  91                               __func__, stat);
  92                        return -EIO;
  93                }
  94                if (!transfer_done && (stat & rdy)) {
  95                        if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  96                                continue;
  97                        sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  98                        sdhci_transfer_pio(host, data);
  99                        data->dest += data->blocksize;
 100                        if (++block >= data->blocks) {
 101                                /* Keep looping until the SDHCI_INT_DATA_END is
 102                                 * cleared, even if we finished sending all the
 103                                 * blocks.
 104                                 */
 105                                transfer_done = true;
 106                                continue;
 107                        }
 108                }
 109#ifdef CONFIG_MMC_SDHCI_SDMA
 110                if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
 111                        sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 112                        start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 113                        start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 114                        sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 115                }
 116#endif
 117                if (timeout-- > 0)
 118                        udelay(10);
 119                else {
 120                        printf("%s: Transfer data timeout\n", __func__);
 121                        return -ETIMEDOUT;
 122                }
 123        } while (!(stat & SDHCI_INT_DATA_END));
 124        return 0;
 125}
 126
 127/*
 128 * No command will be sent by driver if card is busy, so driver must wait
 129 * for card ready state.
 130 * Every time when card is busy after timeout then (last) timeout value will be
 131 * increased twice but only if it doesn't exceed global defined maximum.
 132 * Each function call will use last timeout value.
 133 */
 134#define SDHCI_CMD_MAX_TIMEOUT                   3200
 135#define SDHCI_CMD_DEFAULT_TIMEOUT               100
 136#define SDHCI_READ_STATUS_TIMEOUT               1000
 137
 138#ifdef CONFIG_DM_MMC
 139static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 140                              struct mmc_data *data)
 141{
 142        struct mmc *mmc = mmc_get_mmc_dev(dev);
 143
 144#else
 145static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 146                              struct mmc_data *data)
 147{
 148#endif
 149        struct sdhci_host *host = mmc->priv;
 150        unsigned int stat = 0;
 151        int ret = 0;
 152        int trans_bytes = 0, is_aligned = 1;
 153        u32 mask, flags, mode;
 154        unsigned int time = 0, start_addr = 0;
 155        int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 156        unsigned start = get_timer(0);
 157
 158        /* Timeout unit - ms */
 159        static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 160
 161        if (((host->last_cmd == MMC_CMD_WRITE_MULTIPLE_BLOCK) ||
 162             (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)) &&
 163            (host->quirks & SDHCI_QUIRK_USE_ACMD12) &&
 164            (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION))
 165                return 0;
 166
 167        sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 168        mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 169
 170        /* We shouldn't wait for data inihibit for stop commands, even
 171           though they might use busy signaling */
 172        if ((cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) ||
 173            (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK) ||
 174            (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK_HS200))
 175                mask &= ~SDHCI_DATA_INHIBIT;
 176
 177        while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 178                if (time >= cmd_timeout) {
 179                        printf("%s: MMC: %d busy ", __func__, mmc_dev);
 180                        if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 181                                cmd_timeout += cmd_timeout;
 182                                printf("timeout increasing to: %u ms.\n",
 183                                       cmd_timeout);
 184                        } else {
 185                                puts("timeout.\n");
 186                                return -ECOMM;
 187                        }
 188                }
 189                time++;
 190                udelay(1000);
 191        }
 192
 193        mask = SDHCI_INT_RESPONSE;
 194
 195        /* only buffer read ready interrupt whil tuning */
 196        if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
 197            (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK_HS200))
 198                mask = SDHCI_INT_DATA_AVAIL;
 199
 200        if (!(cmd->resp_type & MMC_RSP_PRESENT))
 201                flags = SDHCI_CMD_RESP_NONE;
 202        else if (cmd->resp_type & MMC_RSP_136)
 203                flags = SDHCI_CMD_RESP_LONG;
 204        else if (cmd->resp_type & MMC_RSP_BUSY) {
 205                flags = SDHCI_CMD_RESP_SHORT_BUSY;
 206                if (data)
 207                        mask |= SDHCI_INT_DATA_END;
 208        } else
 209                flags = SDHCI_CMD_RESP_SHORT;
 210
 211        if (cmd->resp_type & MMC_RSP_CRC)
 212                flags |= SDHCI_CMD_CRC;
 213        if (cmd->resp_type & MMC_RSP_OPCODE)
 214                flags |= SDHCI_CMD_INDEX;
 215        if (data || (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK) ||
 216            (cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK_HS200))
 217                flags |= SDHCI_CMD_DATA;
 218
 219        host->last_cmd = cmd->cmdidx;
 220
 221        /* Set Transfer mode regarding to data flag */
 222        if (data != 0) {
 223                sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 224                mode = SDHCI_TRNS_BLK_CNT_EN;
 225                trans_bytes = data->blocks * data->blocksize;
 226                if (data->blocks > 1)
 227                        mode |= SDHCI_TRNS_MULTI;
 228
 229                if (((cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK) ||
 230                     (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)) &&
 231                    (host->quirks & SDHCI_QUIRK_USE_ACMD12))
 232                        mode |= SDHCI_TRNS_ACMD12;
 233
 234                if (data->flags == MMC_DATA_READ)
 235                        mode |= SDHCI_TRNS_READ;
 236
 237#ifdef CONFIG_MMC_SDHCI_SDMA
 238                if (data->flags == MMC_DATA_READ)
 239                        start_addr = (unsigned long)data->dest;
 240                else
 241                        start_addr = (unsigned long)data->src;
 242                if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 243                                (start_addr & 0x7) != 0x0) {
 244                        is_aligned = 0;
 245                        start_addr = (unsigned long)aligned_buffer;
 246                        if (data->flags != MMC_DATA_READ)
 247                                memcpy(aligned_buffer, data->src, trans_bytes);
 248                }
 249
 250#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 251                /*
 252                 * Always use this bounce-buffer when
 253                 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 254                 */
 255                is_aligned = 0;
 256                start_addr = (unsigned long)aligned_buffer;
 257                if (data->flags != MMC_DATA_READ)
 258                        memcpy(aligned_buffer, data->src, trans_bytes);
 259#endif
 260
 261                sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 262                mode |= SDHCI_TRNS_DMA;
 263#endif
 264                sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 265                                data->blocksize),
 266                                SDHCI_BLOCK_SIZE);
 267                sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 268                sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 269        } else if (cmd->resp_type & MMC_RSP_BUSY) {
 270                sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 271        }
 272
 273        sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 274#ifdef CONFIG_MMC_SDHCI_SDMA
 275        if (data != 0) {
 276                trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
 277                flush_cache(start_addr, trans_bytes);
 278        }
 279#endif
 280        sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 281        start = get_timer(0);
 282        do {
 283                stat = sdhci_readl(host, SDHCI_INT_STATUS);
 284                if (stat & SDHCI_INT_ERROR)
 285                        break;
 286
 287                if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 288                        if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 289                                return 0;
 290                        } else {
 291                                printf("%s: Timeout for status update!\n",
 292                                       __func__);
 293                                return -ETIMEDOUT;
 294                        }
 295                }
 296        } while ((stat & mask) != mask);
 297
 298        if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 299                sdhci_cmd_done(host, cmd);
 300                sdhci_writel(host, mask, SDHCI_INT_STATUS);
 301        } else
 302                ret = -1;
 303
 304        if (!ret && data)
 305                ret = sdhci_transfer_data(host, data, start_addr);
 306
 307        if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 308                udelay(1000);
 309
 310        stat = sdhci_readl(host, SDHCI_INT_STATUS);
 311        sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 312        if (!ret) {
 313                if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 314                                !is_aligned && (data->flags == MMC_DATA_READ))
 315                        memcpy(data->dest, aligned_buffer, trans_bytes);
 316                return 0;
 317        }
 318
 319        sdhci_reset(host, SDHCI_RESET_CMD);
 320        sdhci_reset(host, SDHCI_RESET_DATA);
 321        if (stat & SDHCI_INT_TIMEOUT)
 322                return -ETIMEDOUT;
 323        else
 324                return -ECOMM;
 325}
 326
 327#if CONFIG_IS_ENABLED(DM_MMC)
 328static int sdhci_execute_tuning(struct udevice *dev, u8 opcode)
 329{
 330        struct mmc *mmc = mmc_get_mmc_dev(dev);
 331#else
 332static int sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 333{
 334#endif
 335        struct mmc_cmd cmd;
 336        struct mmc_data data;
 337        u32 ctrl;
 338        int err;
 339        u8 tuning_loop_counter = 40;
 340        struct sdhci_host *host = mmc->priv;
 341
 342        debug("%s\n", __func__);
 343
 344        if (host->platform_execute_tuning) {
 345                err = host->platform_execute_tuning(mmc, opcode);
 346                if (err)
 347                        return err;
 348                return 0;
 349        }
 350
 351        ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
 352        ctrl |= SDHCI_CTRL_EXEC_TUNING;
 353        sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
 354
 355        sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 356        sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 357
 358        do {
 359                cmd.cmdidx = opcode;
 360                cmd.resp_type = MMC_RSP_R1;
 361                cmd.cmdarg = 0;
 362
 363                data.blocksize = 64;
 364                data.blocks = 1;
 365                data.flags = MMC_DATA_READ;
 366
 367                if (tuning_loop_counter == 0)
 368                        break;
 369
 370                tuning_loop_counter--;
 371
 372                if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 373                    mmc->bus_width == 8) {
 374                        data.blocksize = 128;
 375                }
 376
 377                sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 378                                                    data.blocksize),
 379                             SDHCI_BLOCK_SIZE);
 380                sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 381                sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 382
 383#if CONFIG_IS_ENABLED(DM_MMC)
 384                sdhci_send_command(dev, &cmd, &data);
 385#else
 386                sdhci_send_command(mmc, &cmd, &data);
 387#endif
 388                ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
 389
 390                if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 391                        udelay(1);
 392
 393        } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 394
 395        if (tuning_loop_counter < 0) {
 396                ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 397                sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
 398        }
 399
 400        if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 401                debug("%s:Tuning failed\n", __func__);
 402                return -1;
 403        }
 404
 405        /* Enable only interrupts served by the SD controller */
 406        sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 407                     SDHCI_INT_ENABLE);
 408        /* Mask all sdhci interrupt sources */
 409        sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 410
 411        return 0;
 412}
 413
 414static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 415{
 416        struct sdhci_host *host = mmc->priv;
 417        unsigned int div, clk = 0, timeout;
 418
 419        /* Wait max 20 ms */
 420        timeout = 200;
 421        while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 422                           (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 423                if (timeout == 0) {
 424                        printf("%s: Timeout to wait cmd & data inhibit\n",
 425                               __func__);
 426                        return -EBUSY;
 427                }
 428
 429                timeout--;
 430                udelay(100);
 431        }
 432
 433        sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 434
 435        if (clock == 0)
 436                return 0;
 437
 438        if (host->set_delay)
 439                host->set_delay(host);
 440
 441        if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 442                /*
 443                 * Check if the Host Controller supports Programmable Clock
 444                 * Mode.
 445                 */
 446                if (host->clk_mul) {
 447                        for (div = 1; div <= 1024; div++) {
 448                                if ((host->max_clk / div) <= clock)
 449                                        break;
 450                        }
 451
 452                        /*
 453                         * Set Programmable Clock Mode in the Clock
 454                         * Control register.
 455                         */
 456                        clk = SDHCI_PROG_CLOCK_MODE;
 457                        div--;
 458                } else {
 459                        /* Version 3.00 divisors must be a multiple of 2. */
 460                        if (host->max_clk <= clock) {
 461                                div = 1;
 462                        } else {
 463                                for (div = 2;
 464                                     div < SDHCI_MAX_DIV_SPEC_300;
 465                                     div += 2) {
 466                                        if ((host->max_clk / div) <= clock)
 467                                                break;
 468                                }
 469                        }
 470                        div >>= 1;
 471                }
 472        } else {
 473                /* Version 2.00 divisors must be a power of 2. */
 474                for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 475                        if ((host->max_clk / div) <= clock)
 476                                break;
 477                }
 478                div >>= 1;
 479        }
 480
 481        if (host->ops && host->ops->set_clock)
 482                host->ops->set_clock(host, div);
 483
 484        clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 485        clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 486                << SDHCI_DIVIDER_HI_SHIFT;
 487        clk |= SDHCI_CLOCK_INT_EN;
 488        sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 489
 490        /* Wait max 20 ms */
 491        timeout = 20;
 492        while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 493                & SDHCI_CLOCK_INT_STABLE)) {
 494                if (timeout == 0) {
 495                        printf("%s: Internal clock never stabilised.\n",
 496                               __func__);
 497                        return -EBUSY;
 498                }
 499                timeout--;
 500                udelay(1000);
 501        }
 502
 503        clk |= SDHCI_CLOCK_CARD_EN;
 504        sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 505        return 0;
 506}
 507
 508#ifdef CONFIG_DM_MMC
 509static int sdhci_set_voltage(struct udevice *dev)
 510{
 511        struct mmc *mmc = mmc_get_mmc_dev(dev);
 512#else
 513static int sdhci_set_voltage(struct mmc *mmc)
 514{
 515#endif
 516        struct sdhci_host *host = mmc->priv;
 517        u32 reg;
 518        int err;
 519
 520        debug("%s\n", __func__);
 521
 522        reg = (unsigned long)host->ioaddr + SDHCI_PRESENT_STATE;
 523        /* Wait max 20ms for the bits to clear*/
 524        err = wait_for_bit(__func__, (const u32 *)(uintptr_t)reg,
 525                           (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT),
 526                           false, 20, false);
 527        if (err < 0)
 528                return err;
 529
 530        reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 531        reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
 532        sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
 533
 534        /* keep clock gated for 5 msec as per spec */
 535        udelay(5000);
 536
 537        reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
 538        reg |= SDHCI_18V_SIGNAL;
 539        sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
 540
 541        sdhci_set_clock(mmc, mmc->cfg->f_min);
 542
 543        reg = (unsigned long)host->ioaddr + SDHCI_PRESENT_STATE;
 544        /* Wait max 20ms for bits to be clear */
 545        err = wait_for_bit(__func__, (const u32 *)(uintptr_t)reg,
 546                           (SDHCI_CMD_BUSY | SDHCI_DATA_BUSY),
 547                           true, 20, false);
 548        if (err < 0)
 549                return err;
 550
 551        return 0;
 552}
 553
 554#ifdef CONFIG_DM_MMC
 555static int sdhci_set_uhs(struct udevice *dev)
 556{
 557        struct mmc *mmc = mmc_get_mmc_dev(dev);
 558#else
 559static int sdhci_set_uhs(struct mmc *mmc)
 560{
 561#endif
 562        struct sdhci_host *host = mmc->priv;
 563        u32 reg;
 564
 565        debug("%s\n", __func__);
 566        reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
 567        reg &= ~SDHCI_CTRL2_MODE_MASK;
 568        reg |= mmc->uhsmode;
 569        sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
 570
 571        return 0;
 572}
 573
 574static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 575{
 576        u8 pwr = 0;
 577
 578        if (power != (unsigned short)-1) {
 579                switch (1 << power) {
 580                case MMC_VDD_165_195:
 581                        pwr = SDHCI_POWER_180;
 582                        break;
 583                case MMC_VDD_29_30:
 584                case MMC_VDD_30_31:
 585                        pwr = SDHCI_POWER_300;
 586                        break;
 587                case MMC_VDD_32_33:
 588                case MMC_VDD_33_34:
 589                        pwr = SDHCI_POWER_330;
 590                        break;
 591                }
 592        }
 593
 594        if (pwr == 0) {
 595                sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 596                return;
 597        }
 598
 599        pwr |= SDHCI_POWER_ON;
 600
 601        sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 602}
 603
 604#ifdef CONFIG_DM_MMC
 605static int sdhci_set_ios(struct udevice *dev)
 606{
 607        struct mmc *mmc = mmc_get_mmc_dev(dev);
 608#else
 609static int sdhci_set_ios(struct mmc *mmc)
 610{
 611#endif
 612        u32 ctrl;
 613        struct sdhci_host *host = mmc->priv;
 614
 615        if (host->ops && host->ops->set_control_reg)
 616                host->ops->set_control_reg(host);
 617
 618        if (mmc->clock != host->clock)
 619                sdhci_set_clock(mmc, mmc->clock);
 620
 621        /* Set bus width */
 622        ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 623        if (mmc->bus_width == 8) {
 624                ctrl &= ~SDHCI_CTRL_4BITBUS;
 625                if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 626                                (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 627                        ctrl |= SDHCI_CTRL_8BITBUS;
 628        } else {
 629                if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 630                                (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 631                        ctrl &= ~SDHCI_CTRL_8BITBUS;
 632                if (mmc->bus_width == 4)
 633                        ctrl |= SDHCI_CTRL_4BITBUS;
 634                else
 635                        ctrl &= ~SDHCI_CTRL_4BITBUS;
 636        }
 637
 638        if (mmc->clock > 26000000)
 639                ctrl |= SDHCI_CTRL_HISPD;
 640        else
 641                ctrl &= ~SDHCI_CTRL_HISPD;
 642
 643        if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 644                ctrl &= ~SDHCI_CTRL_HISPD;
 645
 646        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 647
 648        /* If available, call the driver specific "post" set_ios() function */
 649        if (host->ops && host->ops->set_ios_post)
 650                host->ops->set_ios_post(host);
 651
 652        return 0;
 653}
 654
 655static int sdhci_init(struct mmc *mmc)
 656{
 657        struct sdhci_host *host = mmc->priv;
 658
 659        sdhci_reset(host, SDHCI_RESET_ALL);
 660
 661        if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 662                aligned_buffer = memalign(8, 512*1024);
 663                if (!aligned_buffer) {
 664                        printf("%s: Aligned buffer alloc failed!!!\n",
 665                               __func__);
 666                        return -ENOMEM;
 667                }
 668        }
 669
 670        sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 671
 672        if (host->ops && host->ops->get_cd)
 673                host->ops->get_cd(host);
 674
 675        /* Enable only interrupts served by the SD controller */
 676        sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 677                     SDHCI_INT_ENABLE);
 678        /* Mask all sdhci interrupt sources */
 679        sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 680
 681        return 0;
 682}
 683
 684#ifdef CONFIG_DM_MMC
 685int sdhci_probe(struct udevice *dev)
 686{
 687        struct mmc *mmc = mmc_get_mmc_dev(dev);
 688
 689        return sdhci_init(mmc);
 690}
 691
 692const struct dm_mmc_ops sdhci_ops = {
 693        .send_cmd       = sdhci_send_command,
 694        .set_ios        = sdhci_set_ios,
 695        .set_voltage    = sdhci_set_voltage,
 696        .set_uhs        = sdhci_set_uhs,
 697        .execute_tuning = sdhci_execute_tuning,
 698};
 699#else
 700static const struct mmc_ops sdhci_ops = {
 701        .send_cmd       = sdhci_send_command,
 702        .set_ios        = sdhci_set_ios,
 703        .init           = sdhci_init,
 704        .set_voltage    = sdhci_set_voltage,
 705        .set_uhs        = sdhci_set_uhs,
 706        .execute_tuning = sdhci_execute_tuning,
 707};
 708#endif
 709
 710int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 711                u32 f_max, u32 f_min)
 712{
 713        u32 caps;
 714        u32 caps_1 = 0;
 715
 716        caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 717
 718#ifdef CONFIG_MMC_SDHCI_SDMA
 719        if (!(caps & SDHCI_CAN_DO_SDMA)) {
 720                printf("%s: Your controller doesn't support SDMA!!\n",
 721                       __func__);
 722                return -EINVAL;
 723        }
 724#endif
 725        if (host->quirks & SDHCI_QUIRK_REG32_RW)
 726                host->version =
 727                        sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 728        else
 729                host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 730
 731        cfg->name = host->name;
 732#ifndef CONFIG_DM_MMC
 733        cfg->ops = &sdhci_ops;
 734#endif
 735
 736        /* Check whether the clock multiplier is supported or not */
 737        if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 738                caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 739                host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 740                                SDHCI_CLOCK_MUL_SHIFT;
 741        }
 742
 743        if (host->max_clk == 0) {
 744                if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 745                        host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 746                                SDHCI_CLOCK_BASE_SHIFT;
 747                else
 748                        host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 749                                SDHCI_CLOCK_BASE_SHIFT;
 750                host->max_clk *= 1000000;
 751                if (host->clk_mul)
 752                        host->max_clk *= host->clk_mul;
 753        }
 754        if (host->max_clk == 0) {
 755                printf("%s: Hardware doesn't specify base clock frequency\n",
 756                       __func__);
 757                return -EINVAL;
 758        }
 759        if (f_max && (f_max < host->max_clk))
 760                cfg->f_max = f_max;
 761        else
 762                cfg->f_max = host->max_clk;
 763        if (f_min)
 764                cfg->f_min = f_min;
 765        else {
 766                if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 767                        cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 768                else
 769                        cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 770        }
 771        cfg->voltages = 0;
 772        if (caps & SDHCI_CAN_VDD_330)
 773                cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 774        if (caps & SDHCI_CAN_VDD_300)
 775                cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 776        if (caps & SDHCI_CAN_VDD_180)
 777                cfg->voltages |= MMC_VDD_165_195;
 778
 779        if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 780                cfg->voltages |= host->voltages;
 781
 782        cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 783
 784        /* Since Host Controller Version3.0 */
 785        if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 786                if (!(caps & SDHCI_CAN_DO_8BIT))
 787                        cfg->host_caps &= ~MMC_MODE_8BIT;
 788        }
 789
 790        if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 791                caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 792
 793        if (!(cfg->voltages & MMC_VDD_165_195) ||
 794            (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 795                caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 796                            SDHCI_SUPPORT_DDR50);
 797
 798        if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 799                      SDHCI_SUPPORT_DDR50))
 800                cfg->host_caps |= MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25;
 801
 802        if (caps_1 & SDHCI_SUPPORT_SDR104) {
 803                cfg->host_caps |= MMC_MODE_UHS_SDR104 | MMC_MODE_UHS_SDR50;
 804                /*
 805                 * SD3.0: SDR104 is supported so (for eMMC) the caps2
 806                 * field can be promoted to support HS200.
 807                 */
 808                cfg->host_caps |= MMC_MODE_HS200;
 809        } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 810                cfg->host_caps |= MMC_MODE_UHS_SDR50;
 811        }
 812
 813        if (caps_1 & SDHCI_SUPPORT_DDR50)
 814                cfg->host_caps |= MMC_MODE_UHS_DDR50;
 815
 816        if (caps_1 & SDHCI_USE_SDR50_TUNING)
 817                cfg->host_caps |= MMC_MODE_NEEDS_TUNING;
 818
 819        if (host->host_caps)
 820                cfg->host_caps |= host->host_caps;
 821
 822        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 823
 824        if (caps_1 & SDHCI_SUPPORT_SDR104) {
 825                cfg->host_caps |= MMC_MODE_UHS_SDR104 | MMC_MODE_UHS_SDR50;
 826                /*
 827                 * SD3.0: SDR104 is supported so (for eMMC) the caps2
 828                 * field can be promoted to support HS200.
 829                 */
 830                cfg->host_caps |= MMC_MODE_HS200;
 831        } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 832                cfg->host_caps |= MMC_MODE_UHS_SDR50;
 833        }
 834
 835        if (caps_1 & SDHCI_SUPPORT_DDR50)
 836                cfg->host_caps |= MMC_MODE_UHS_DDR50;
 837
 838        if (caps_1 & SDHCI_USE_SDR50_TUNING)
 839                cfg->host_caps |= MMC_MODE_NEEDS_TUNING;
 840
 841        if (host->host_caps)
 842                cfg->host_caps |= host->host_caps;
 843
 844        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 845
 846        return 0;
 847}
 848
 849#ifdef CONFIG_BLK
 850int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 851{
 852        return mmc_bind(dev, mmc, cfg);
 853}
 854#else
 855int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 856{
 857        int ret;
 858
 859        ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 860        if (ret)
 861                return ret;
 862
 863        host->mmc = mmc_create(&host->cfg, host);
 864        if (host->mmc == NULL) {
 865                printf("%s: mmc create fail!\n", __func__);
 866                return -ENOMEM;
 867        }
 868
 869        return 0;
 870}
 871#endif
 872