1/* 2 * USB HOST XHCI Controller 3 * 4 * Based on xHCI host controller driver in linux-kernel 5 * by Sarah Sharp. 6 * 7 * Copyright (C) 2008 Intel Corp. 8 * Author: Sarah Sharp 9 * 10 * Copyright (C) 2013 Samsung Electronics Co.Ltd 11 * Authors: Vivek Gautam <gautam.vivek@samsung.com> 12 * Vikas Sajjan <vikas.sajjan@samsung.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17#ifndef HOST_XHCI_H_ 18#define HOST_XHCI_H_ 19 20#include <asm/types.h> 21#include <asm/cache.h> 22#include <asm/io.h> 23#include <linux/list.h> 24#include <linux/compat.h> 25 26#define MAX_EP_CTX_NUM 31 27#define XHCI_ALIGNMENT 64 28/* Generic timeout for XHCI events */ 29#define XHCI_TIMEOUT 5000 30/* Max number of USB devices for any host controller - limit in section 6.1 */ 31#define MAX_HC_SLOTS 256 32/* Section 5.3.3 - MaxPorts */ 33#define MAX_HC_PORTS 255 34 35/* Up to 16 ms to halt an HC */ 36#define XHCI_MAX_HALT_USEC (16*1000) 37 38#define XHCI_MAX_RESET_USEC (250*1000) 39 40/* 41 * These bits are Read Only (RO) and should be saved and written to the 42 * registers: 0, 3, 10:13, 30 43 * connect status, over-current status, port speed, and device removable. 44 * connect status and port speed are also sticky - meaning they're in 45 * the AUX well and they aren't changed by a hot, warm, or cold reset. 46 */ 47#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) 48/* 49 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 50 * bits 5:8, 9, 14:15, 25:27 51 * link state, port power, port indicator state, "wake on" enable state 52 */ 53#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) 54/* 55 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 56 * bit 4 (port reset) 57 */ 58#define XHCI_PORT_RW1S ((1 << 4)) 59/* 60 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 61 * bits 1, 17, 18, 19, 20, 21, 22, 23 62 * port enable/disable, and 63 * change bits: connect, PED, 64 * warm port reset changed (reserved zero for USB 2.0 ports), 65 * over-current, reset, link state, and L1 change 66 */ 67#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) 68/* 69 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 70 * latched in 71 */ 72#define XHCI_PORT_RW ((1 << 16)) 73/* 74 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 75 * bits 2, 24, 28:31 76 */ 77#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) 78 79/* 80 * XHCI Register Space. 81 */ 82struct xhci_hccr { 83 uint32_t cr_capbase; 84 uint32_t cr_hcsparams1; 85 uint32_t cr_hcsparams2; 86 uint32_t cr_hcsparams3; 87 uint32_t cr_hccparams; 88 uint32_t cr_dboff; 89 uint32_t cr_rtsoff; 90 91/* hc_capbase bitmasks */ 92/* bits 7:0 - how long is the Capabilities register */ 93#define HC_LENGTH(p) XHCI_HC_LENGTH(p) 94/* bits 31:16 */ 95#define HC_VERSION(p) (((p) >> 16) & 0xffff) 96 97/* HCSPARAMS1 - hcs_params1 - bitmasks */ 98/* bits 0:7, Max Device Slots */ 99#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 100#define HCS_SLOTS_MASK 0xff 101/* bits 8:18, Max Interrupters */ 102#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 103/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 104#define HCS_MAX_PORTS_SHIFT 24 105#define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT) 106#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) 107 108/* HCSPARAMS2 - hcs_params2 - bitmasks */ 109/* bits 0:3, frames or uframes that SW needs to queue transactions 110 * ahead of the HW to meet periodic deadlines */ 111#define HCS_IST(p) (((p) >> 0) & 0xf) 112/* bits 4:7, max number of Event Ring segments */ 113#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 114/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 115/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 116/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 117#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 118 119/* HCSPARAMS3 - hcs_params3 - bitmasks */ 120/* bits 0:7, Max U1 to U0 latency for the roothub ports */ 121#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 122/* bits 16:31, Max U2 to U0 latency for the roothub ports */ 123#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 124 125/* HCCPARAMS - hcc_params - bitmasks */ 126/* true: HC can use 64-bit address pointers */ 127#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 128/* true: HC can do bandwidth negotiation */ 129#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 130/* true: HC uses 64-byte Device Context structures 131 * FIXME 64-byte context structures aren't supported yet. 132 */ 133#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 134/* true: HC has port power switches */ 135#define HCC_PPC(p) ((p) & (1 << 3)) 136/* true: HC has port indicators */ 137#define HCS_INDICATOR(p) ((p) & (1 << 4)) 138/* true: HC has Light HC Reset Capability */ 139#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 140/* true: HC supports latency tolerance messaging */ 141#define HCC_LTC(p) ((p) & (1 << 6)) 142/* true: no secondary Stream ID Support */ 143#define HCC_NSS(p) ((p) & (1 << 7)) 144/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 145#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 146/* Extended Capabilities pointer from PCI base - section 5.3.6 */ 147#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 148 149/* db_off bitmask - bits 0:1 reserved */ 150#define DBOFF_MASK (~0x3) 151 152/* run_regs_off bitmask - bits 0:4 reserved */ 153#define RTSOFF_MASK (~0x1f) 154 155}; 156 157struct xhci_hcor_port_regs { 158 volatile uint32_t or_portsc; 159 volatile uint32_t or_portpmsc; 160 volatile uint32_t or_portli; 161 volatile uint32_t reserved_3; 162}; 163 164struct xhci_hcor { 165 volatile uint32_t or_usbcmd; 166 volatile uint32_t or_usbsts; 167 volatile uint32_t or_pagesize; 168 volatile uint32_t reserved_0[2]; 169 volatile uint32_t or_dnctrl; 170 volatile uint64_t or_crcr; 171 volatile uint32_t reserved_1[4]; 172 volatile uint64_t or_dcbaap; 173 volatile uint32_t or_config; 174 volatile uint32_t reserved_2[241]; 175 struct xhci_hcor_port_regs portregs[MAX_HC_PORTS]; 176}; 177 178/* USBCMD - USB command - command bitmasks */ 179/* start/stop HC execution - do not write unless HC is halted*/ 180#define CMD_RUN XHCI_CMD_RUN 181/* Reset HC - resets internal HC state machine and all registers (except 182 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 183 * The xHCI driver must reinitialize the xHC after setting this bit. 184 */ 185#define CMD_RESET (1 << 1) 186/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 187#define CMD_EIE XHCI_CMD_EIE 188/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 189#define CMD_HSEIE XHCI_CMD_HSEIE 190/* bits 4:6 are reserved (and should be preserved on writes). */ 191/* light reset (port status stays unchanged) - reset completed when this is 0 */ 192#define CMD_LRESET (1 << 7) 193/* host controller save/restore state. */ 194#define CMD_CSS (1 << 8) 195#define CMD_CRS (1 << 9) 196/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 197#define CMD_EWE XHCI_CMD_EWE 198/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 199 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 200 * '0' means the xHC can power it off if all ports are in the disconnect, 201 * disabled, or powered-off state. 202 */ 203#define CMD_PM_INDEX (1 << 11) 204/* bits 12:31 are reserved (and should be preserved on writes). */ 205 206/* USBSTS - USB status - status bitmasks */ 207/* HC not running - set to 1 when run/stop bit is cleared. */ 208#define STS_HALT XHCI_STS_HALT 209/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 210#define STS_FATAL (1 << 2) 211/* event interrupt - clear this prior to clearing any IP flags in IR set*/ 212#define STS_EINT (1 << 3) 213/* port change detect */ 214#define STS_PORT (1 << 4) 215/* bits 5:7 reserved and zeroed */ 216/* save state status - '1' means xHC is saving state */ 217#define STS_SAVE (1 << 8) 218/* restore state status - '1' means xHC is restoring state */ 219#define STS_RESTORE (1 << 9) 220/* true: save or restore error */ 221#define STS_SRE (1 << 10) 222/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 223#define STS_CNR XHCI_STS_CNR 224/* true: internal Host Controller Error - SW needs to reset and reinitialize */ 225#define STS_HCE (1 << 12) 226/* bits 13:31 reserved and should be preserved */ 227 228/* 229 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 230 * Generate a device notification event when the HC sees a transaction with a 231 * notification type that matches a bit set in this bit field. 232 */ 233#define DEV_NOTE_MASK (0xffff) 234#define ENABLE_DEV_NOTE(x) (1 << (x)) 235/* Most of the device notification types should only be used for debug. 236 * SW does need to pay attention to function wake notifications. 237 */ 238#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 239 240/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 241/* bit 0 is the command ring cycle state */ 242/* stop ring operation after completion of the currently executing command */ 243#define CMD_RING_PAUSE (1 << 1) 244/* stop ring immediately - abort the currently executing command */ 245#define CMD_RING_ABORT (1 << 2) 246/* true: command ring is running */ 247#define CMD_RING_RUNNING (1 << 3) 248/* bits 4:5 reserved and should be preserved */ 249/* Command Ring pointer - bit mask for the lower 32 bits. */ 250#define CMD_RING_RSVD_BITS (0x3f) 251 252/* CONFIG - Configure Register - config_reg bitmasks */ 253/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 254#define MAX_DEVS(p) ((p) & 0xff) 255/* bits 8:31 - reserved and should be preserved */ 256 257/* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 258/* true: device connected */ 259#define PORT_CONNECT (1 << 0) 260/* true: port enabled */ 261#define PORT_PE (1 << 1) 262/* bit 2 reserved and zeroed */ 263/* true: port has an over-current condition */ 264#define PORT_OC (1 << 3) 265/* true: port reset signaling asserted */ 266#define PORT_RESET (1 << 4) 267/* Port Link State - bits 5:8 268 * A read gives the current link PM state of the port, 269 * a write with Link State Write Strobe set sets the link state. 270 */ 271#define PORT_PLS_MASK (0xf << 5) 272#define XDEV_U0 (0x0 << 5) 273#define XDEV_U2 (0x2 << 5) 274#define XDEV_U3 (0x3 << 5) 275#define XDEV_RESUME (0xf << 5) 276/* true: port has power (see HCC_PPC) */ 277#define PORT_POWER (1 << 9) 278/* bits 10:13 indicate device speed: 279 * 0 - undefined speed - port hasn't be initialized by a reset yet 280 * 1 - full speed 281 * 2 - low speed 282 * 3 - high speed 283 * 4 - super speed 284 * 5-15 reserved 285 */ 286#define DEV_SPEED_MASK (0xf << 10) 287#define XDEV_FS (0x1 << 10) 288#define XDEV_LS (0x2 << 10) 289#define XDEV_HS (0x3 << 10) 290#define XDEV_SS (0x4 << 10) 291#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 292#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 293#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 294#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 295#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 296/* Bits 20:23 in the Slot Context are the speed for the device */ 297#define SLOT_SPEED_FS (XDEV_FS << 10) 298#define SLOT_SPEED_LS (XDEV_LS << 10) 299#define SLOT_SPEED_HS (XDEV_HS << 10) 300#define SLOT_SPEED_SS (XDEV_SS << 10) 301/* Port Indicator Control */ 302#define PORT_LED_OFF (0 << 14) 303#define PORT_LED_AMBER (1 << 14) 304#define PORT_LED_GREEN (2 << 14) 305#define PORT_LED_MASK (3 << 14) 306/* Port Link State Write Strobe - set this when changing link state */ 307#define PORT_LINK_STROBE (1 << 16) 308/* true: connect status change */ 309#define PORT_CSC (1 << 17) 310/* true: port enable change */ 311#define PORT_PEC (1 << 18) 312/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 313 * into an enabled state, and the device into the default state. A "warm" reset 314 * also resets the link, forcing the device through the link training sequence. 315 * SW can also look at the Port Reset register to see when warm reset is done. 316 */ 317#define PORT_WRC (1 << 19) 318/* true: over-current change */ 319#define PORT_OCC (1 << 20) 320/* true: reset change - 1 to 0 transition of PORT_RESET */ 321#define PORT_RC (1 << 21) 322/* port link status change - set on some port link state transitions: 323 * Transition Reason 324 * -------------------------------------------------------------------------- 325 * - U3 to Resume Wakeup signaling from a device 326 * - Resume to Recovery to U0 USB 3.0 device resume 327 * - Resume to U0 USB 2.0 device resume 328 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 329 * - U3 to U0 Software resume of USB 2.0 device complete 330 * - U2 to U0 L1 resume of USB 2.1 device complete 331 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 332 * - U0 to disabled L1 entry error with USB 2.1 device 333 * - Any state to inactive Error on USB 3.0 port 334 */ 335#define PORT_PLC (1 << 22) 336/* port configure error change - port failed to configure its link partner */ 337#define PORT_CEC (1 << 23) 338/* bit 24 reserved */ 339/* wake on connect (enable) */ 340#define PORT_WKCONN_E (1 << 25) 341/* wake on disconnect (enable) */ 342#define PORT_WKDISC_E (1 << 26) 343/* wake on over-current (enable) */ 344#define PORT_WKOC_E (1 << 27) 345/* bits 28:29 reserved */ 346/* true: device is removable - for USB 3.0 roothub emulation */ 347#define PORT_DEV_REMOVE (1 << 30) 348/* Initiate a warm port reset - complete when PORT_WRC is '1' */ 349#define PORT_WR (1 << 31) 350 351/* We mark duplicate entries with -1 */ 352#define DUPLICATE_ENTRY ((u8)(-1)) 353 354/* Port Power Management Status and Control - port_power_base bitmasks */ 355/* Inactivity timer value for transitions into U1, in microseconds. 356 * Timeout can be up to 127us. 0xFF means an infinite timeout. 357 */ 358#define PORT_U1_TIMEOUT(p) ((p) & 0xff) 359/* Inactivity timer value for transitions into U2 */ 360#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 361/* Bits 24:31 for port testing */ 362 363/* USB2 Protocol PORTSPMSC */ 364#define PORT_L1S_MASK 7 365#define PORT_L1S_SUCCESS 1 366#define PORT_RWE (1 << 3) 367#define PORT_HIRD(p) (((p) & 0xf) << 4) 368#define PORT_HIRD_MASK (0xf << 4) 369#define PORT_L1DS(p) (((p) & 0xff) << 8) 370#define PORT_HLE (1 << 16) 371 372/** 373* struct xhci_intr_reg - Interrupt Register Set 374* @irq_pending: IMAN - Interrupt Management Register. Used to enable 375* interrupts and check for pending interrupts. 376* @irq_control: IMOD - Interrupt Moderation Register. 377* Used to throttle interrupts. 378* @erst_size: Number of segments in the 379 Event Ring Segment Table (ERST). 380* @erst_base: ERST base address. 381* @erst_dequeue: Event ring dequeue pointer. 382* 383* Each interrupter (defined by a MSI-X vector) has an event ring and an Event 384* Ring Segment Table (ERST) associated with it. 385* The event ring is comprised of multiple segments of the same size. 386* The HC places events on the ring and "updates the Cycle bit in the TRBs to 387* indicate to software the current position of the Enqueue Pointer." 388* The HCD (Linux) processes those events and updates the dequeue pointer. 389*/ 390struct xhci_intr_reg { 391 volatile __le32 irq_pending; 392 volatile __le32 irq_control; 393 volatile __le32 erst_size; 394 volatile __le32 rsvd; 395 volatile __le64 erst_base; 396 volatile __le64 erst_dequeue; 397}; 398 399/* irq_pending bitmasks */ 400#define ER_IRQ_PENDING(p) ((p) & 0x1) 401/* bits 2:31 need to be preserved */ 402/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 403#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 404#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 405#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 406 407/* irq_control bitmasks */ 408/* Minimum interval between interrupts (in 250ns intervals). The interval 409 * between interrupts will be longer if there are no events on the event ring. 410 * Default is 4000 (1 ms). 411 */ 412#define ER_IRQ_INTERVAL_MASK (0xffff) 413/* Counter used to count down the time to the next interrupt - HW use only */ 414#define ER_IRQ_COUNTER_MASK (0xffff << 16) 415 416/* erst_size bitmasks */ 417/* Preserve bits 16:31 of erst_size */ 418#define ERST_SIZE_MASK (0xffff << 16) 419 420/* erst_dequeue bitmasks */ 421/* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 422 * where the current dequeue pointer lies. This is an optional HW hint. 423 */ 424#define ERST_DESI_MASK (0x7) 425/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 426 * a work queue (or delayed service routine)? 427 */ 428#define ERST_EHB (1 << 3) 429#define ERST_PTR_MASK (0xf) 430 431/** 432 * struct xhci_run_regs 433 * @microframe_index: MFINDEX - current microframe number 434 * 435 * Section 5.5 Host Controller Runtime Registers: 436 * "Software should read and write these registers using only Dword (32 bit) 437 * or larger accesses" 438 */ 439struct xhci_run_regs { 440 __le32 microframe_index; 441 __le32 rsvd[7]; 442 struct xhci_intr_reg ir_set[128]; 443}; 444 445/** 446 * struct doorbell_array 447 * 448 * Bits 0 - 7: Endpoint target 449 * Bits 8 - 15: RsvdZ 450 * Bits 16 - 31: Stream ID 451 * 452 * Section 5.6 453 */ 454struct xhci_doorbell_array { 455 volatile __le32 doorbell[256]; 456}; 457 458#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 459#define DB_VALUE_HOST 0x00000000 460 461/** 462 * struct xhci_protocol_caps 463 * @revision: major revision, minor revision, capability ID, 464 * and next capability pointer. 465 * @name_string: Four ASCII characters to say which spec this xHC 466 * follows, typically "USB ". 467 * @port_info: Port offset, count, and protocol-defined information. 468 */ 469struct xhci_protocol_caps { 470 u32 revision; 471 u32 name_string; 472 u32 port_info; 473}; 474 475#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 476#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 477#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 478 479/** 480 * struct xhci_container_ctx 481 * @type: Type of context. Used to calculated offsets to contained contexts. 482 * @size: Size of the context data 483 * @bytes: The raw context data given to HW 484 * 485 * Represents either a Device or Input context. Holds a pointer to the raw 486 * memory used for the context (bytes). 487 */ 488struct xhci_container_ctx { 489 unsigned type; 490#define XHCI_CTX_TYPE_DEVICE 0x1 491#define XHCI_CTX_TYPE_INPUT 0x2 492 493 int size; 494 u8 *bytes; 495}; 496 497/** 498 * struct xhci_slot_ctx 499 * @dev_info: Route string, device speed, hub info, and last valid endpoint 500 * @dev_info2: Max exit latency for device number, root hub port number 501 * @tt_info: tt_info is used to construct split transaction tokens 502 * @dev_state: slot state and device address 503 * 504 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 505 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 506 * reserved at the end of the slot context for HC internal use. 507 */ 508struct xhci_slot_ctx { 509 __le32 dev_info; 510 __le32 dev_info2; 511 __le32 tt_info; 512 __le32 dev_state; 513 /* offset 0x10 to 0x1f reserved for HC internal use */ 514 __le32 reserved[4]; 515}; 516 517/* dev_info bitmasks */ 518/* Route String - 0:19 */ 519#define ROUTE_STRING_MASK (0xfffff) 520/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 521#define DEV_SPEED (0xf << 20) 522/* bit 24 reserved */ 523/* Is this LS/FS device connected through a HS hub? - bit 25 */ 524#define DEV_MTT (0x1 << 25) 525/* Set if the device is a hub - bit 26 */ 526#define DEV_HUB (0x1 << 26) 527/* Index of the last valid endpoint context in this device context - 27:31 */ 528#define LAST_CTX_MASK (0x1f << 27) 529#define LAST_CTX(p) ((p) << 27) 530#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 531#define SLOT_FLAG (1 << 0) 532#define EP0_FLAG (1 << 1) 533 534/* dev_info2 bitmasks */ 535/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 536#define MAX_EXIT (0xffff) 537/* Root hub port number that is needed to access the USB device */ 538#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 539#define ROOT_HUB_PORT_MASK (0xff) 540#define ROOT_HUB_PORT_SHIFT (16) 541#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 542/* Maximum number of ports under a hub device */ 543#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 544 545/* tt_info bitmasks */ 546/* 547 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 548 * The Slot ID of the hub that isolates the high speed signaling from 549 * this low or full-speed device. '0' if attached to root hub port. 550 */ 551#define TT_SLOT(p) (((p) & 0xff) << 0) 552/* 553 * The number of the downstream facing port of the high-speed hub 554 * '0' if the device is not low or full speed. 555 */ 556#define TT_PORT(p) (((p) & 0xff) << 8) 557#define TT_THINK_TIME(p) (((p) & 0x3) << 16) 558 559/* dev_state bitmasks */ 560/* USB device address - assigned by the HC */ 561#define DEV_ADDR_MASK (0xff) 562/* bits 8:26 reserved */ 563/* Slot state */ 564#define SLOT_STATE (0x1f << 27) 565#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 566 567#define SLOT_STATE_DISABLED 0 568#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 569#define SLOT_STATE_DEFAULT 1 570#define SLOT_STATE_ADDRESSED 2 571#define SLOT_STATE_CONFIGURED 3 572 573/** 574 * struct xhci_ep_ctx 575 * @ep_info: endpoint state, streams, mult, and interval information. 576 * @ep_info2: information on endpoint type, max packet size, max burst size, 577 * error count, and whether the HC will force an event for all 578 * transactions. 579 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 580 * defines one stream, this points to the endpoint transfer ring. 581 * Otherwise, it points to a stream context array, which has a 582 * ring pointer for each flow. 583 * @tx_info: 584 * Average TRB lengths for the endpoint ring and 585 * max payload within an Endpoint Service Interval Time (ESIT). 586 * 587 * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context 588 * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes 589 * reserved at the end of the endpoint context for HC internal use. 590 */ 591struct xhci_ep_ctx { 592 __le32 ep_info; 593 __le32 ep_info2; 594 __le64 deq; 595 __le32 tx_info; 596 /* offset 0x14 - 0x1f reserved for HC internal use */ 597 __le32 reserved[3]; 598}; 599 600/* ep_info bitmasks */ 601/* 602 * Endpoint State - bits 0:2 603 * 0 - disabled 604 * 1 - running 605 * 2 - halted due to halt condition - ok to manipulate endpoint ring 606 * 3 - stopped 607 * 4 - TRB error 608 * 5-7 - reserved 609 */ 610#define EP_STATE_MASK (0xf) 611#define EP_STATE_DISABLED 0 612#define EP_STATE_RUNNING 1 613#define EP_STATE_HALTED 2 614#define EP_STATE_STOPPED 3 615#define EP_STATE_ERROR 4 616/* Mult - Max number of burtst within an interval, in EP companion desc. */ 617#define EP_MULT(p) (((p) & 0x3) << 8) 618#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 619/* bits 10:14 are Max Primary Streams */ 620/* bit 15 is Linear Stream Array */ 621/* Interval - period between requests to an endpoint - 125u increments. */ 622#define EP_INTERVAL(p) (((p) & 0xff) << 16) 623#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 624#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 625#define EP_MAXPSTREAMS_MASK (0x1f << 10) 626#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 627/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 628#define EP_HAS_LSA (1 << 15) 629 630/* ep_info2 bitmasks */ 631/* 632 * Force Event - generate transfer events for all TRBs for this endpoint 633 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 634 */ 635#define FORCE_EVENT (0x1) 636#define ERROR_COUNT(p) (((p) & 0x3) << 1) 637#define ERROR_COUNT_SHIFT (1) 638#define ERROR_COUNT_MASK (0x3) 639#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 640#define EP_TYPE(p) ((p) << 3) 641#define EP_TYPE_SHIFT (3) 642#define ISOC_OUT_EP 1 643#define BULK_OUT_EP 2 644#define INT_OUT_EP 3 645#define CTRL_EP 4 646#define ISOC_IN_EP 5 647#define BULK_IN_EP 6 648#define INT_IN_EP 7 649/* bit 6 reserved */ 650/* bit 7 is Host Initiate Disable - for disabling stream selection */ 651#define MAX_BURST(p) (((p)&0xff) << 8) 652#define MAX_BURST_MASK (0xff) 653#define MAX_BURST_SHIFT (8) 654#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 655#define MAX_PACKET(p) (((p)&0xffff) << 16) 656#define MAX_PACKET_MASK (0xffff) 657#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 658#define MAX_PACKET_SHIFT (16) 659 660/* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 661 * USB2.0 spec 9.6.6. 662 */ 663#define GET_MAX_PACKET(p) ((p) & 0x7ff) 664 665/* tx_info bitmasks */ 666#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 667#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 668#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 669#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 670 671/* deq bitmasks */ 672#define EP_CTX_CYCLE_MASK (1 << 0) 673 674 675/** 676 * struct xhci_input_control_context 677 * Input control context; see section 6.2.5. 678 * 679 * @drop_context: set the bit of the endpoint context you want to disable 680 * @add_context: set the bit of the endpoint context you want to enable 681 */ 682struct xhci_input_control_ctx { 683 volatile __le32 drop_flags; 684 volatile __le32 add_flags; 685 __le32 rsvd2[6]; 686}; 687 688 689/** 690 * struct xhci_device_context_array 691 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 692 */ 693struct xhci_device_context_array { 694 /* 64-bit device addresses; we only write 32-bit addresses */ 695 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 696}; 697/* TODO: write function to set the 64-bit device DMA address */ 698/* 699 * TODO: change this to be dynamically sized at HC mem init time since the HC 700 * might not be able to handle the maximum number of devices possible. 701 */ 702 703 704struct xhci_transfer_event { 705 /* 64-bit buffer address, or immediate data */ 706 __le64 buffer; 707 __le32 transfer_len; 708 /* This field is interpreted differently based on the type of TRB */ 709 volatile __le32 flags; 710}; 711 712/* Transfer event TRB length bit mask */ 713/* bits 0:23 */ 714#define EVENT_TRB_LEN(p) ((p) & 0xffffff) 715 716/** Transfer Event bit fields **/ 717#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 718 719/* Completion Code - only applicable for some types of TRBs */ 720#define COMP_CODE_MASK (0xff << 24) 721#define COMP_CODE_SHIFT (24) 722#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 723 724typedef enum { 725 COMP_SUCCESS = 1, 726 /* Data Buffer Error */ 727 COMP_DB_ERR, /* 2 */ 728 /* Babble Detected Error */ 729 COMP_BABBLE, /* 3 */ 730 /* USB Transaction Error */ 731 COMP_TX_ERR, /* 4 */ 732 /* TRB Error - some TRB field is invalid */ 733 COMP_TRB_ERR, /* 5 */ 734 /* Stall Error - USB device is stalled */ 735 COMP_STALL, /* 6 */ 736 /* Resource Error - HC doesn't have memory for that device configuration */ 737 COMP_ENOMEM, /* 7 */ 738 /* Bandwidth Error - not enough room in schedule for this dev config */ 739 COMP_BW_ERR, /* 8 */ 740 /* No Slots Available Error - HC ran out of device slots */ 741 COMP_ENOSLOTS, /* 9 */ 742 /* Invalid Stream Type Error */ 743 COMP_STREAM_ERR, /* 10 */ 744 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 745 COMP_EBADSLT, /* 11 */ 746 /* Endpoint Not Enabled Error */ 747 COMP_EBADEP,/* 12 */ 748 /* Short Packet */ 749 COMP_SHORT_TX, /* 13 */ 750 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 751 COMP_UNDERRUN, /* 14 */ 752 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 753 COMP_OVERRUN, /* 15 */ 754 /* Virtual Function Event Ring Full Error */ 755 COMP_VF_FULL, /* 16 */ 756 /* Parameter Error - Context parameter is invalid */ 757 COMP_EINVAL, /* 17 */ 758 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 759 COMP_BW_OVER,/* 18 */ 760 /* Context State Error - illegal context state transition requested */ 761 COMP_CTX_STATE,/* 19 */ 762 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 763 COMP_PING_ERR,/* 20 */ 764 /* Event Ring is full */ 765 COMP_ER_FULL,/* 21 */ 766 /* Incompatible Device Error */ 767 COMP_DEV_ERR,/* 22 */ 768 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 769 COMP_MISSED_INT,/* 23 */ 770 /* Successfully stopped command ring */ 771 COMP_CMD_STOP, /* 24 */ 772 /* Successfully aborted current command and stopped command ring */ 773 COMP_CMD_ABORT, /* 25 */ 774 /* Stopped - transfer was terminated by a stop endpoint command */ 775 COMP_STOP,/* 26 */ 776 /* Same as COMP_EP_STOPPED, but the transferred length in the event 777 * is invalid */ 778 COMP_STOP_INVAL, /* 27*/ 779 /* Control Abort Error - Debug Capability - control pipe aborted */ 780 COMP_DBG_ABORT, /* 28 */ 781 /* Max Exit Latency Too Large Error */ 782 COMP_MEL_ERR,/* 29 */ 783 /* TRB type 30 reserved */ 784 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 785 COMP_BUFF_OVER = 31, 786 /* Event Lost Error - xHC has an "internal event overrun condition" */ 787 COMP_ISSUES, /* 32 */ 788 /* Undefined Error - reported when other error codes don't apply */ 789 COMP_UNKNOWN, /* 33 */ 790 /* Invalid Stream ID Error */ 791 COMP_STRID_ERR, /* 34 */ 792 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 793 COMP_2ND_BW_ERR, /* 35 */ 794 /* Split Transaction Error */ 795 COMP_SPLIT_ERR /* 36 */ 796 797} xhci_comp_code; 798 799struct xhci_link_trb { 800 /* 64-bit segment pointer*/ 801 volatile __le64 segment_ptr; 802 volatile __le32 intr_target; 803 volatile __le32 control; 804}; 805 806/* control bitfields */ 807#define LINK_TOGGLE (0x1 << 1) 808 809/* Command completion event TRB */ 810struct xhci_event_cmd { 811 /* Pointer to command TRB, or the value passed by the event data trb */ 812 volatile __le64 cmd_trb; 813 volatile __le32 status; 814 volatile __le32 flags; 815}; 816 817/* flags bitmasks */ 818/* bits 16:23 are the virtual function ID */ 819/* bits 24:31 are the slot ID */ 820#define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) 821#define TRB_TO_SLOT_ID_SHIFT (24) 822#define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) 823#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 824#define SLOT_ID_FOR_TRB_MASK (0xff) 825#define SLOT_ID_FOR_TRB_SHIFT (24) 826 827/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 828#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 829#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 830 831#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 832#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 833#define LAST_EP_INDEX 30 834 835/* Set TR Dequeue Pointer command TRB fields */ 836#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 837#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 838 839 840/* Port Status Change Event TRB fields */ 841/* Port ID - bits 31:24 */ 842#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 843#define PORT_ID_SHIFT (24) 844#define PORT_ID_MASK (0xff << PORT_ID_SHIFT) 845 846/* Normal TRB fields */ 847/* transfer_len bitmasks - bits 0:16 */ 848#define TRB_LEN(p) ((p) & 0x1ffff) 849#define TRB_LEN_MASK (0x1ffff) 850/* Interrupter Target - which MSI-X vector to target the completion event at */ 851#define TRB_INTR_TARGET_SHIFT (22) 852#define TRB_INTR_TARGET_MASK (0x3ff) 853#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 854#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 855#define TRB_TBC(p) (((p) & 0x3) << 7) 856#define TRB_TLBPC(p) (((p) & 0xf) << 16) 857 858/* Cycle bit - indicates TRB ownership by HC or HCD */ 859#define TRB_CYCLE (1<<0) 860/* 861 * Force next event data TRB to be evaluated before task switch. 862 * Used to pass OS data back after a TD completes. 863 */ 864#define TRB_ENT (1<<1) 865/* Interrupt on short packet */ 866#define TRB_ISP (1<<2) 867/* Set PCIe no snoop attribute */ 868#define TRB_NO_SNOOP (1<<3) 869/* Chain multiple TRBs into a TD */ 870#define TRB_CHAIN (1<<4) 871/* Interrupt on completion */ 872#define TRB_IOC (1<<5) 873/* The buffer pointer contains immediate data */ 874#define TRB_IDT (1<<6) 875 876/* Block Event Interrupt */ 877#define TRB_BEI (1<<9) 878 879/* Control transfer TRB specific fields */ 880#define TRB_DIR_IN (1<<16) 881#define TRB_TX_TYPE(p) ((p) << 16) 882#define TRB_TX_TYPE_SHIFT (16) 883#define TRB_DATA_OUT 2 884#define TRB_DATA_IN 3 885 886/* Isochronous TRB specific fields */ 887#define TRB_SIA (1 << 31) 888 889struct xhci_generic_trb { 890 volatile __le32 field[4]; 891}; 892 893union xhci_trb { 894 struct xhci_link_trb link; 895 struct xhci_transfer_event trans_event; 896 struct xhci_event_cmd event_cmd; 897 struct xhci_generic_trb generic; 898}; 899 900/* TRB bit mask */ 901#define TRB_TYPE_BITMASK (0xfc00) 902#define TRB_TYPE(p) ((p) << 10) 903#define TRB_TYPE_SHIFT (10) 904#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 905 906/* TRB type IDs */ 907typedef enum { 908 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 909 TRB_NORMAL = 1, 910 /* setup stage for control transfers */ 911 TRB_SETUP, /* 2 */ 912 /* data stage for control transfers */ 913 TRB_DATA, /* 3 */ 914 /* status stage for control transfers */ 915 TRB_STATUS, /* 4 */ 916 /* isoc transfers */ 917 TRB_ISOC, /* 5 */ 918 /* TRB for linking ring segments */ 919 TRB_LINK, /* 6 */ 920 /* TRB for EVENT DATA */ 921 TRB_EVENT_DATA, /* 7 */ 922 /* Transfer Ring No-op (not for the command ring) */ 923 TRB_TR_NOOP, /* 8 */ 924 /* Command TRBs */ 925 /* Enable Slot Command */ 926 TRB_ENABLE_SLOT, /* 9 */ 927 /* Disable Slot Command */ 928 TRB_DISABLE_SLOT, /* 10 */ 929 /* Address Device Command */ 930 TRB_ADDR_DEV, /* 11 */ 931 /* Configure Endpoint Command */ 932 TRB_CONFIG_EP, /* 12 */ 933 /* Evaluate Context Command */ 934 TRB_EVAL_CONTEXT, /* 13 */ 935 /* Reset Endpoint Command */ 936 TRB_RESET_EP, /* 14 */ 937 /* Stop Transfer Ring Command */ 938 TRB_STOP_RING, /* 15 */ 939 /* Set Transfer Ring Dequeue Pointer Command */ 940 TRB_SET_DEQ, /* 16 */ 941 /* Reset Device Command */ 942 TRB_RESET_DEV, /* 17 */ 943 /* Force Event Command (opt) */ 944 TRB_FORCE_EVENT, /* 18 */ 945 /* Negotiate Bandwidth Command (opt) */ 946 TRB_NEG_BANDWIDTH, /* 19 */ 947 /* Set Latency Tolerance Value Command (opt) */ 948 TRB_SET_LT, /* 20 */ 949 /* Get port bandwidth Command */ 950 TRB_GET_BW, /* 21 */ 951 /* Force Header Command - generate a transaction or link management packet */ 952 TRB_FORCE_HEADER, /* 22 */ 953 /* No-op Command - not for transfer rings */ 954 TRB_CMD_NOOP, /* 23 */ 955 /* TRB IDs 24-31 reserved */ 956 /* Event TRBS */ 957 /* Transfer Event */ 958 TRB_TRANSFER = 32, 959 /* Command Completion Event */ 960 TRB_COMPLETION, /* 33 */ 961 /* Port Status Change Event */ 962 TRB_PORT_STATUS, /* 34 */ 963 /* Bandwidth Request Event (opt) */ 964 TRB_BANDWIDTH_EVENT, /* 35 */ 965 /* Doorbell Event (opt) */ 966 TRB_DOORBELL, /* 36 */ 967 /* Host Controller Event */ 968 TRB_HC_EVENT, /* 37 */ 969 /* Device Notification Event - device sent function wake notification */ 970 TRB_DEV_NOTE, /* 38 */ 971 /* MFINDEX Wrap Event - microframe counter wrapped */ 972 TRB_MFINDEX_WRAP, /* 39 */ 973 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 974 /* Nec vendor-specific command completion event. */ 975 TRB_NEC_CMD_COMP = 48, /* 48 */ 976 /* Get NEC firmware revision. */ 977 TRB_NEC_GET_FW, /* 49 */ 978} trb_type; 979 980#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 981/* Above, but for __le32 types -- can avoid work by swapping constants: */ 982#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 983 cpu_to_le32(TRB_TYPE(TRB_LINK))) 984#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 985 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 986 987/* 988 * TRBS_PER_SEGMENT must be a multiple of 4, 989 * since the command ring is 64-byte aligned. 990 * It must also be greater than 16. 991 */ 992#define TRBS_PER_SEGMENT 64 993/* Allow two commands + a link TRB, along with any reserved command TRBs */ 994#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 995#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 996/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 997 * Change this if you change TRBS_PER_SEGMENT! 998 */ 999#define SEGMENT_SHIFT 10 1000/* TRB buffer pointers can't cross 64KB boundaries */
1001#define TRB_MAX_BUFF_SHIFT 16 1002#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1003 1004struct xhci_segment { 1005 union xhci_trb *trbs; 1006 /* private to HCD */ 1007 struct xhci_segment *next; 1008}; 1009 1010struct xhci_ring { 1011 struct xhci_segment *first_seg; 1012 union xhci_trb *enqueue; 1013 struct xhci_segment *enq_seg; 1014 union xhci_trb *dequeue; 1015 struct xhci_segment *deq_seg; 1016 /* 1017 * Write the cycle state into the TRB cycle field to give ownership of 1018 * the TRB to the host controller (if we are the producer), or to check 1019 * if we own the TRB (if we are the consumer). See section 4.9.1. 1020 */ 1021 volatile u32 cycle_state; 1022 unsigned int num_segs; 1023}; 1024 1025struct xhci_erst_entry { 1026 /* 64-bit event ring segment address */ 1027 __le64 seg_addr; 1028 __le32 seg_size; 1029 /* Set to zero */ 1030 __le32 rsvd; 1031}; 1032 1033struct xhci_erst { 1034 struct xhci_erst_entry *entries; 1035 unsigned int num_entries; 1036 /* Num entries the ERST can contain */ 1037 unsigned int erst_size; 1038}; 1039 1040struct xhci_scratchpad { 1041 u64 *sp_array; 1042}; 1043 1044/* 1045 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1046 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1047 * meaning 64 ring segments. 1048 * Initial allocated size of the ERST, in number of entries */ 1049#define ERST_NUM_SEGS 1 1050/* Initial number of event segment rings allocated */ 1051#define ERST_ENTRIES 1 1052/* Initial allocated size of the ERST, in number of entries */ 1053#define ERST_SIZE 64 1054/* Poll every 60 seconds */ 1055#define POLL_TIMEOUT 60 1056/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1057#define XHCI_STOP_EP_CMD_TIMEOUT 5 1058/* XXX: Make these module parameters */ 1059 1060struct xhci_virt_ep { 1061 struct xhci_ring *ring; 1062 unsigned int ep_state; 1063#define SET_DEQ_PENDING (1 << 0) 1064#define EP_HALTED (1 << 1) /* For stall handling */ 1065#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 1066/* Transitioning the endpoint to using streams, don't enqueue URBs */ 1067#define EP_GETTING_STREAMS (1 << 3) 1068#define EP_HAS_STREAMS (1 << 4) 1069/* Transitioning the endpoint to not using streams, don't enqueue URBs */ 1070#define EP_GETTING_NO_STREAMS (1 << 5) 1071}; 1072 1073#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 1074 1075struct xhci_virt_device { 1076 struct usb_device *udev; 1077 /* 1078 * Commands to the hardware are passed an "input context" that 1079 * tells the hardware what to change in its data structures. 1080 * The hardware will return changes in an "output context" that 1081 * software must allocate for the hardware. We need to keep 1082 * track of input and output contexts separately because 1083 * these commands might fail and we don't trust the hardware. 1084 */ 1085 struct xhci_container_ctx *out_ctx; 1086 /* Used for addressing devices and configuration changes */ 1087 struct xhci_container_ctx *in_ctx; 1088 /* Rings saved to ensure old alt settings can be re-instated */ 1089#define XHCI_MAX_RINGS_CACHED 31 1090 struct xhci_virt_ep eps[31]; 1091}; 1092 1093/* TODO: copied from ehci.h - can be refactored? */ 1094/* xHCI spec says all registers are little endian */ 1095static inline unsigned int xhci_readl(uint32_t volatile *regs) 1096{ 1097 return readl(regs); 1098} 1099 1100static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) 1101{ 1102 writel(val, regs); 1103} 1104 1105/* 1106 * Registers should always be accessed with double word or quad word accesses. 1107 * Some xHCI implementations may support 64-bit address pointers. Registers 1108 * with 64-bit address pointers should be written to with dword accesses by 1109 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1110 * xHCI implementations that do not support 64-bit address pointers will ignore 1111 * the high dword, and write order is irrelevant. 1112 */ 1113static inline u64 xhci_readq(__le64 volatile *regs) 1114{ 1115#if BITS_PER_LONG == 64 1116 return readq(regs); 1117#else 1118 __u32 *ptr = (__u32 *)regs; 1119 u64 val_lo = readl(ptr); 1120 u64 val_hi = readl(ptr + 1); 1121 return val_lo + (val_hi << 32); 1122#endif 1123} 1124 1125static inline void xhci_writeq(__le64 volatile *regs, const u64 val) 1126{ 1127#if BITS_PER_LONG == 64 1128 writeq(val, regs); 1129#else 1130 __u32 *ptr = (__u32 *)regs; 1131 u32 val_lo = lower_32_bits(val); 1132 /* FIXME */ 1133 u32 val_hi = upper_32_bits(val); 1134 writel(val_lo, ptr); 1135 writel(val_hi, ptr + 1); 1136#endif 1137} 1138 1139int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, 1140 struct xhci_hcor **ret_hcor); 1141void xhci_hcd_stop(int index); 1142 1143 1144/************************************************************* 1145 EXTENDED CAPABILITY DEFINITIONS 1146*************************************************************/ 1147/* Up to 16 ms to halt an HC */ 1148#define XHCI_MAX_HALT_USEC (16*1000) 1149/* HC not running - set to 1 when run/stop bit is cleared. */ 1150#define XHCI_STS_HALT (1 << 0) 1151 1152/* HCCPARAMS offset from PCI base address */ 1153#define XHCI_HCC_PARAMS_OFFSET 0x10 1154/* HCCPARAMS contains the first extended capability pointer */ 1155#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 1156 1157/* Command and Status registers offset from the Operational Registers address */ 1158#define XHCI_CMD_OFFSET 0x00 1159#define XHCI_STS_OFFSET 0x04 1160 1161#define XHCI_MAX_EXT_CAPS 50 1162 1163/* Capability Register */ 1164/* bits 7:0 - how long is the Capabilities register */ 1165#define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) 1166 1167/* Extended capability register fields */ 1168#define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) 1169#define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) 1170#define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) 1171/* Extended capability IDs - ID 0 reserved */ 1172#define XHCI_EXT_CAPS_LEGACY 1 1173#define XHCI_EXT_CAPS_PROTOCOL 2 1174#define XHCI_EXT_CAPS_PM 3 1175#define XHCI_EXT_CAPS_VIRT 4 1176#define XHCI_EXT_CAPS_ROUTE 5 1177/* IDs 6-9 reserved */ 1178#define XHCI_EXT_CAPS_DEBUG 10 1179/* USB Legacy Support Capability - section 7.1.1 */ 1180#define XHCI_HC_BIOS_OWNED (1 << 16) 1181#define XHCI_HC_OS_OWNED (1 << 24) 1182 1183/* USB Legacy Support Capability - section 7.1.1 */ 1184/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1185#define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 1186 1187/* USB Legacy Support Control and Status Register - section 7.1.2 */ 1188/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1189#define XHCI_LEGACY_CONTROL_OFFSET (0x04) 1190/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 1191#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 1192 1193/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 1194#define XHCI_L1C (1 << 16) 1195 1196/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 1197#define XHCI_HLC (1 << 19) 1198 1199/* command register values to disable interrupts and halt the HC */ 1200/* start/stop HC execution - do not write unless HC is halted*/ 1201#define XHCI_CMD_RUN (1 << 0) 1202/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 1203#define XHCI_CMD_EIE (1 << 2) 1204/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 1205#define XHCI_CMD_HSEIE (1 << 3) 1206/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 1207#define XHCI_CMD_EWE (1 << 10) 1208 1209#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 1210 1211/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 1212#define XHCI_STS_CNR (1 << 11) 1213 1214struct xhci_ctrl { 1215#ifdef CONFIG_DM_USB 1216 struct udevice *dev; 1217#endif 1218 struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ 1219 struct xhci_hcor *hcor; 1220 struct xhci_doorbell_array *dba; 1221 struct xhci_run_regs *run_regs; 1222 struct xhci_device_context_array *dcbaa \ 1223 __attribute__ ((aligned(ARCH_DMA_MINALIGN))); 1224 struct xhci_ring *event_ring; 1225 struct xhci_ring *cmd_ring; 1226 struct xhci_ring *transfer_ring; 1227 struct xhci_segment *seg; 1228 struct xhci_intr_reg *ir_set; 1229 struct xhci_erst erst; 1230 struct xhci_erst_entry entry[ERST_NUM_SEGS]; 1231 struct xhci_scratchpad *scratchpad; 1232 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1233 int rootdev; 1234}; 1235 1236unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); 1237struct xhci_input_control_ctx 1238 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1239struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, 1240 struct xhci_container_ctx *ctx); 1241struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, 1242 struct xhci_container_ctx *ctx, 1243 unsigned int ep_index); 1244void xhci_endpoint_copy(struct xhci_ctrl *ctrl, 1245 struct xhci_container_ctx *in_ctx, 1246 struct xhci_container_ctx *out_ctx, 1247 unsigned int ep_index); 1248void xhci_slot_copy(struct xhci_ctrl *ctrl, 1249 struct xhci_container_ctx *in_ctx, 1250 struct xhci_container_ctx *out_ctx); 1251void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, 1252 struct usb_device *udev, int hop_portnr); 1253void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, 1254 u32 slot_id, u32 ep_index, trb_type cmd); 1255void xhci_acknowledge_event(struct xhci_ctrl *ctrl); 1256union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); 1257int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, 1258 int length, void *buffer); 1259int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, 1260 struct devrequest *req, int length, void *buffer); 1261int xhci_check_maxpacket(struct usb_device *udev); 1262void xhci_flush_cache(uintptr_t addr, u32 type_len); 1263void xhci_inval_cache(uintptr_t addr, u32 type_len); 1264void xhci_cleanup(struct xhci_ctrl *ctrl); 1265struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs); 1266int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id); 1267int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, 1268 struct xhci_hcor *hcor); 1269 1270/** 1271 * xhci_deregister() - Unregister an XHCI controller 1272 * 1273 * @dev: Controller device 1274 * @return 0 if registered, -ve on error 1275 */ 1276int xhci_deregister(struct udevice *dev); 1277 1278/** 1279 * xhci_register() - Register a new XHCI controller 1280 * 1281 * @dev: Controller device 1282 * @hccr: Host controller control registers 1283 * @hcor: Not sure what this means 1284 * @return 0 if registered, -ve on error 1285 */ 1286int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, 1287 struct xhci_hcor *hcor); 1288 1289extern struct dm_usb_ops xhci_usb_ops; 1290 1291struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); 1292 1293#endif /* HOST_XHCI_H_ */ 1294