LXR uboot/include/configs/cm

   1/*
   2 * cm_t43.h
   3 *
   4 * Copyright (C) 2015 Compulab, Ltd.
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#ifndef __CONFIG_CM_T43_H
  10#define __CONFIG_CM_T43_H
  11
  12#define CONFIG_CM_T43
  13#define CONFIG_ARCH_CPU_INIT
  14#define CONFIG_MAX_RAM_BANK_SIZE        (2048 << 20)    /* 2GB */
  15#define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
  16
  17#include <asm/arch/omap.h>
  18
  19/* Serial support */
  20#define CONFIG_SYS_NS16550_SERIAL
  21#define CONFIG_SYS_NS16550_CLK          48000000
  22#define CONFIG_SYS_NS16550_COM1         0x44e09000
  23#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
  24#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  25#endif
  26
  27/* NAND support */
  28#define CONFIG_SYS_NAND_ONFI_DETECTION
  29#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  30#define CONFIG_SYS_NAND_PAGE_SIZE       2048
  31#define CONFIG_SYS_NAND_OOBSIZE         64
  32#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
  33#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  34#define CONFIG_SYS_NAND_ECCSIZE         512
  35#define CONFIG_SYS_NAND_ECCBYTES        14
  36#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
  37#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
  38                                         CONFIG_SYS_NAND_PAGE_SIZE)
  39#define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
  40                                         10, 11, 12, 13, 14, 15, 16, 17, \
  41                                         18, 19, 20, 21, 22, 23, 24, 25, \
  42                                         26, 27, 28, 29, 30, 31, 32, 33, \
  43                                         34, 35, 36, 37, 38, 39, 40, 41, \
  44                                         42, 43, 44, 45, 46, 47, 48, 49, \
  45                                         50, 51, 52, 53, 54, 55, 56, 57, }
  46
  47/* CPSW Ethernet support */
  48#define CONFIG_DRIVER_TI_CPSW
  49#define CONFIG_MII
  50#define CONFIG_BOOTP_DEFAULT
  51#define CONFIG_BOOTP_SEND_HOSTNAME
  52#define CONFIG_BOOTP_GATEWAY
  53#define CONFIG_PHY_ATHEROS
  54#define CONFIG_SYS_RX_ETH_BUFFER        64
  55
  56/* USB support */
  57#define CONFIG_USB_XHCI_OMAP
  58#define CONFIG_OMAP_USB_PHY
  59#define CONFIG_AM437X_USB2PHY2_HOST
  60
  61/* SPI Flash support */
  62#define CONFIG_TI_SPI_MMAP
  63#define CONFIG_SF_DEFAULT_SPEED         48000000
  64#define CONFIG_DEFAULT_SPI_MODE         SPI_MODE_3
  65
  66/* Power */
  67#define CONFIG_POWER
  68#define CONFIG_POWER_I2C
  69#define CONFIG_POWER_TPS65218
  70
  71/* Enabling L2 Cache */
  72#define CONFIG_SYS_L2_PL310
  73#define CONFIG_SYS_PL310_BASE           0x48242000
  74
  75/*
  76 * Since SPL did pll and ddr initialization for us,
  77 * we don't need to do it twice.
  78 */
  79#if !defined(CONFIG_SPL_BUILD)
  80#define CONFIG_SKIP_LOWLEVEL_INIT
  81#endif
  82
  83#define CONFIG_HSMMC2_8BIT
  84
  85#include <configs/ti_armv7_omap.h>
  86#undef CONFIG_SYS_MONITOR_LEN
  87
  88#define CONFIG_ENV_SIZE                 (16 * 1024)
  89#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  90
  91#define V_OSCK                          24000000  /* Clock output from T2 */
  92#define V_SCLK                          (V_OSCK)
  93
  94#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
  95#define CONFIG_ENV_OFFSET               (768 * 1024)
  96#define CONFIG_ENV_SPI_MAX_HZ           48000000
  97
  98#define CONFIG_EXTRA_ENV_SETTINGS \
  99        "loadaddr=0x80200000\0" \
 100        "fdtaddr=0x81200000\0" \
 101        "bootm_size=0x8000000\0" \
 102        "autoload=no\0" \
 103        "console=ttyO0,115200n8\0" \
 104        "fdtfile=am437x-sb-som-t43.dtb\0" \
 105        "kernel=zImage-cm-t43\0" \
 106        "bootscr=bootscr.img\0" \
 107        "emmcroot=/dev/mmcblk0p2 rw\0" \
 108        "emmcrootfstype=ext4 rootwait\0" \
 109        "emmcargs=setenv bootargs console=${console} " \
 110                "root=${emmcroot} " \
 111                "rootfstype=${emmcrootfstype}\0" \
 112        "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
 113        "bootscript=echo Running bootscript from mmc ...; " \
 114                "source ${loadaddr}\0" \
 115        "emmcboot=echo Booting from emmc ... && " \
 116                "run emmcargs && " \
 117                "load mmc 1 ${loadaddr} ${kernel} && " \
 118                "load mmc 1 ${fdtaddr} ${fdtfile} && " \
 119                "bootz ${loadaddr} - ${fdtaddr}\0"
 120
 121#define CONFIG_BOOTCOMMAND \
 122        "mmc dev 0; " \
 123        "if mmc rescan; then " \
 124                "if run loadbootscript; then " \
 125                        "run bootscript; " \
 126                "fi; " \
 127        "fi; " \
 128        "mmc dev 1; " \
 129        "if mmc rescan; then " \
 130                "run emmcboot; " \
 131        "fi;"
 132
 133#define CONFIG_CONS_INDEX               1
 134
 135/* SPL defines. */
 136#define CONFIG_SPL_TEXT_BASE            0x40300350
 137#define CONFIG_SYS_SPL_ARGS_ADDR        (CONFIG_SYS_SDRAM_BASE + (128 << 20))
 138#define CONFIG_SYS_SPI_U_BOOT_OFFS      (256 * 1024)
 139#define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 140#define CONFIG_SPL_SPI_LOAD
 141
 142/* EEPROM */
 143#define CONFIG_ENV_EEPROM_IS_ON_I2C
 144#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 145#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 146#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 147#define CONFIG_SYS_EEPROM_SIZE                  256
 148
 149#endif  /* __CONFIG_CM_T43_H */
 150