LXR uboot/include/configs/ls1043a

   1/*
   2 * Copyright (C) 2015 Freescale Semiconductor
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __LS1043A_COMMON_H
   8#define __LS1043A_COMMON_H
   9
  10/* SPL build */
  11#ifdef CONFIG_SPL_BUILD
  12#define SPL_NO_FMAN
  13#define SPL_NO_DSPI
  14#define SPL_NO_PCIE
  15#define SPL_NO_ENV
  16#define SPL_NO_MISC
  17#define SPL_NO_USB
  18#define SPL_NO_SATA
  19#define SPL_NO_QE
  20#define SPL_NO_EEPROM
  21#endif
  22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  23#define SPL_NO_MMC
  24#endif
  25#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
  26#define SPL_NO_IFC
  27#endif
  28
  29#define CONFIG_REMAKE_ELF
  30#define CONFIG_FSL_LAYERSCAPE
  31#define CONFIG_MP
  32#define CONFIG_GICV2
  33
  34#include <asm/arch/stream_id_lsch2.h>
  35#include <asm/arch/config.h>
  36
  37/* Link Definitions */
  38#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  39
  40#define CONFIG_SUPPORT_RAW_INITRD
  41
  42#define CONFIG_SKIP_LOWLEVEL_INIT
  43
  44#define CONFIG_VERY_BIG_RAM
  45#define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  46#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  47#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  48#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  49
  50#define CPU_RELEASE_ADDR               secondary_boot_func
  51
  52/* Generic Timer Definitions */
  53#define COUNTER_FREQUENCY               25000000        /* 25MHz */
  54
  55/* Size of malloc() pool */
  56#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  57
  58/* Serial Port */
  59#define CONFIG_CONS_INDEX               1
  60#define CONFIG_SYS_NS16550_SERIAL
  61#define CONFIG_SYS_NS16550_REG_SIZE     1
  62#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
  63
  64#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  65
  66/* SD boot SPL */
  67#ifdef CONFIG_SD_BOOT
  68#define CONFIG_SPL_FRAMEWORK
  69#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  70
  71#define CONFIG_SPL_TEXT_BASE            0x10000000
  72#define CONFIG_SPL_MAX_SIZE             0x17000
  73#define CONFIG_SPL_STACK                0x1001e000
  74#define CONFIG_SPL_PAD_TO               0x1d000
  75
  76#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  77                                        CONFIG_SPL_BSS_MAX_SIZE)
  78#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  79#define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  80#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  81
  82#ifdef CONFIG_SECURE_BOOT
  83#define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  84/*
  85 * HDR would be appended at end of image and copied to DDR along
  86 * with U-Boot image. Here u-boot max. size is 512K. So if binary
  87 * size increases then increase this size in case of secure boot as
  88 * it uses raw u-boot image instead of fit image.
  89 */
  90#define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  91#else
  92#define CONFIG_SYS_MONITOR_LEN          0x100000
  93#endif /* ifdef CONFIG_SECURE_BOOT */
  94#endif
  95
  96/* NAND SPL */
  97#ifdef CONFIG_NAND_BOOT
  98#define CONFIG_SPL_PBL_PAD
  99#define CONFIG_SPL_FRAMEWORK
 100#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 101#define CONFIG_SPL_TEXT_BASE            0x10000000
 102#define CONFIG_SPL_MAX_SIZE             0x1a000
 103#define CONFIG_SPL_STACK                0x1001d000
 104#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 105#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 106#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 107#define CONFIG_SPL_BSS_START_ADDR       0x80100000
 108#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 109#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 110
 111#ifdef CONFIG_SECURE_BOOT
 112#define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 113#endif /* ifdef CONFIG_SECURE_BOOT */
 114
 115#ifdef CONFIG_U_BOOT_HDR_SIZE
 116/*
 117 * HDR would be appended at end of image and copied to DDR along
 118 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 119 * size increases then increase this size in case of secure boot as
 120 * it uses raw u-boot image instead of fit image.
 121 */
 122#define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 123#else
 124#define CONFIG_SYS_MONITOR_LEN          0x100000
 125#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 126
 127#endif
 128
 129/* IFC */
 130#ifndef SPL_NO_IFC
 131#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 132#define CONFIG_FSL_IFC
 133/*
 134 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 135 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 136 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 137 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 138 */
 139#define CONFIG_SYS_FLASH_BASE                   0x60000000
 140#define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 141#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 142
 143#ifdef CONFIG_MTD_NOR_FLASH
 144#define CONFIG_FLASH_CFI_DRIVER
 145#define CONFIG_SYS_FLASH_CFI
 146#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 147#define CONFIG_SYS_FLASH_QUIET_TEST
 148#define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 149#endif
 150#endif
 151#endif
 152
 153/* I2C */
 154#define CONFIG_SYS_I2C
 155#define CONFIG_SYS_I2C_MXC
 156#define CONFIG_SYS_I2C_MXC_I2C1
 157#define CONFIG_SYS_I2C_MXC_I2C2
 158#define CONFIG_SYS_I2C_MXC_I2C3
 159#define CONFIG_SYS_I2C_MXC_I2C4
 160
 161/* PCIe */
 162#ifndef SPL_NO_PCIE
 163#define CONFIG_PCIE1            /* PCIE controller 1 */
 164#define CONFIG_PCIE2            /* PCIE controller 2 */
 165#define CONFIG_PCIE3            /* PCIE controller 3 */
 166
 167#ifdef CONFIG_PCI
 168#define CONFIG_PCI_SCAN_SHOW
 169#endif
 170#endif
 171
 172/* Command line configuration */
 173
 174/*  MMC  */
 175#ifndef SPL_NO_MMC
 176#ifdef CONFIG_MMC
 177#define CONFIG_FSL_ESDHC
 178#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 179#endif
 180#endif
 181
 182/*  DSPI  */
 183#ifndef SPL_NO_DSPI
 184#define CONFIG_FSL_DSPI
 185#ifdef CONFIG_FSL_DSPI
 186#define CONFIG_DM_SPI_FLASH
 187#define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 188#define CONFIG_SPI_FLASH_SST            /* cs1 */
 189#define CONFIG_SPI_FLASH_EON            /* cs2 */
 190#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 191#define CONFIG_SF_DEFAULT_BUS           1
 192#define CONFIG_SF_DEFAULT_CS            0
 193#endif
 194#endif
 195#endif
 196
 197/* FMan ucode */
 198#ifndef SPL_NO_FMAN
 199#define CONFIG_SYS_DPAA_FMAN
 200#ifdef CONFIG_SYS_DPAA_FMAN
 201#define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 202
 203#ifdef CONFIG_NAND_BOOT
 204/* Store Fman ucode at offeset 0x900000(72 blocks). */
 205#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 206#define CONFIG_SYS_FMAN_FW_ADDR         (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 207#elif defined(CONFIG_SD_BOOT)
 208/*
 209 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 210 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 211 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
 212 */
 213#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 214#define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x4800)
 215#define CONFIG_SYS_QE_FW_ADDR           (512 * 0x4a08)
 216#elif defined(CONFIG_QSPI_BOOT)
 217#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 218#define CONFIG_SYS_FMAN_FW_ADDR         0x40900000
 219#define CONFIG_ENV_SPI_BUS              0
 220#define CONFIG_ENV_SPI_CS               0
 221#define CONFIG_ENV_SPI_MAX_HZ           1000000
 222#define CONFIG_ENV_SPI_MODE             0x03
 223#else
 224#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 225/* FMan fireware Pre-load address */
 226#define CONFIG_SYS_FMAN_FW_ADDR         0x60900000
 227#define CONFIG_SYS_QE_FW_ADDR           0x60940000
 228#endif
 229#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 230#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 231#endif
 232#endif
 233
 234/* Miscellaneous configurable options */
 235#define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 236
 237#define CONFIG_HWCONFIG
 238#define HWCONFIG_BUFFER_SIZE            128
 239
 240#ifndef SPL_NO_MISC
 241#include <config_distro_defaults.h>
 242#ifndef CONFIG_SPL_BUILD
 243#define BOOT_TARGET_DEVICES(func) \
 244        func(MMC, mmc, 0) \
 245        func(USB, usb, 0)
 246#include <config_distro_bootcmd.h>
 247#endif
 248
 249/* Initial environment variables */
 250#define CONFIG_EXTRA_ENV_SETTINGS               \
 251        "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 252        "fdt_high=0xffffffffffffffff\0"         \
 253        "initrd_high=0xffffffffffffffff\0"      \
 254        "fdt_addr=0x64f00000\0"                 \
 255        "kernel_addr=0x61000000\0"              \
 256        "scriptaddr=0x80000000\0"               \
 257        "scripthdraddr=0x80080000\0"            \
 258        "fdtheader_addr_r=0x80100000\0"         \
 259        "kernelheader_addr_r=0x80200000\0"      \
 260        "kernel_addr_r=0x81000000\0"            \
 261        "fdt_addr_r=0x90000000\0"               \
 262        "load_addr=0xa0000000\0"                \
 263        "kernelheader_addr=0x60800000\0"        \
 264        "kernel_size=0x2800000\0"               \
 265        "kernelheader_size=0x40000\0"           \
 266        "kernel_addr_sd=0x8000\0"               \
 267        "kernel_size_sd=0x14000\0"              \
 268        "kernelhdr_addr_sd=0x4000\0"            \
 269        "kernelhdr_size_sd=0x10\0"              \
 270        "console=ttyS0,115200\0"                \
 271        "boot_os=y\0"                           \
 272        "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"        \
 273        BOOTENV                                 \
 274        "boot_scripts=ls1043ardb_boot.scr\0"    \
 275        "boot_script_hdr=hdr_ls1043ardb_bs.out\0"       \
 276        "scan_dev_for_boot_part="               \
 277                "part list ${devtype} ${devnum} devplist; "     \
 278                "env exists devplist || setenv devplist 1; "    \
 279                "for distro_bootpart in ${devplist}; do "       \
 280                        "if fstype ${devtype} "                 \
 281                                "${devnum}:${distro_bootpart} " \
 282                                "bootfstype; then "             \
 283                                "run scan_dev_for_boot; "       \
 284                        "fi; "                                  \
 285                "done\0"                        \
 286        "scan_dev_for_boot="                                    \
 287                "echo Scanning ${devtype} "                     \
 288                        "${devnum}:${distro_bootpart}...; "     \
 289                "for prefix in ${boot_prefixes}; do "           \
 290                        "run scan_dev_for_scripts; "            \
 291                "done;\0"                                       \
 292        "boot_a_script="                                        \
 293                "load ${devtype} ${devnum}:${distro_bootpart} " \
 294                        "${scriptaddr} ${prefix}${script}; "    \
 295                "env exists secureboot && load ${devtype} "     \
 296                        "${devnum}:${distro_bootpart} "         \
 297                        "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 298                        "&& esbc_validate ${scripthdraddr};"    \
 299                "source ${scriptaddr}\0"                        \
 300        "qspi_bootcmd=echo Trying load from qspi..;"    \
 301                "sf probe && sf read $load_addr "       \
 302                "$kernel_addr $kernel_size; env exists secureboot "     \
 303                "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 304                "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 305                "bootm $load_addr#$board\0"     \
 306        "nor_bootcmd=echo Trying load from nor..;"      \
 307                "cp.b $kernel_addr $load_addr " \
 308                "$kernel_size; env exists secureboot "  \
 309                "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 310                "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 311                "bootm $load_addr#$board\0"         \
 312        "sd_bootcmd=echo Trying load from SD ..;"       \
 313                "mmcinfo; mmc read $load_addr "         \
 314                "$kernel_addr_sd $kernel_size_sd && "     \
 315                "env exists secureboot && mmc read $kernelheader_addr_r "               \
 316                "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 317                " && esbc_validate ${kernelheader_addr_r};"     \
 318                "bootm $load_addr#$board\0"
 319
 320
 321#undef CONFIG_BOOTCOMMAND
 322#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 323#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 324                           "env exists secureboot && esbc_halt;"
 325#elif defined(CONFIG_SD_BOOT)
 326#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
 327                           "env exists secureboot && esbc_halt;"
 328#else
 329#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 330                           "env exists secureboot && esbc_halt;"
 331#endif
 332#endif
 333
 334/* Monitor Command Prompt */
 335#define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 336#define CONFIG_SYS_LONGHELP
 337
 338#ifndef SPL_NO_MISC
 339#ifndef CONFIG_CMDLINE_EDITING
 340#define CONFIG_CMDLINE_EDITING          1
 341#endif
 342#endif
 343
 344#define CONFIG_AUTO_COMPLETE
 345#define CONFIG_SYS_MAXARGS              64      /* max command args */
 346
 347#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 348
 349#include <asm/arch/soc.h>
 350
 351#endif /* __LS1043A_COMMON_H */
 352