LXR uboot/include/phy.h

   1/*
   2 * Copyright 2011 Freescale Semiconductor, Inc.
   3 *      Andy Fleming <afleming@gmail.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 *
   7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   8 */
   9
  10#ifndef _PHY_H
  11#define _PHY_H
  12
  13#include <linux/list.h>
  14#include <linux/mii.h>
  15#include <linux/ethtool.h>
  16#include <linux/mdio.h>
  17
  18#define PHY_FIXED_ID            0xa5a55a5a
  19
  20#define PHY_MAX_ADDR 32
  21
  22#define PHY_FLAG_BROKEN_RESET   (1 << 0) /* soft reset not supported */
  23
  24#define PHY_DEFAULT_FEATURES    (SUPPORTED_Autoneg | \
  25                                 SUPPORTED_TP | \
  26                                 SUPPORTED_MII)
  27
  28#define PHY_10BT_FEATURES       (SUPPORTED_10baseT_Half | \
  29                                 SUPPORTED_10baseT_Full)
  30
  31#define PHY_100BT_FEATURES      (SUPPORTED_100baseT_Half | \
  32                                 SUPPORTED_100baseT_Full)
  33
  34#define PHY_1000BT_FEATURES     (SUPPORTED_1000baseT_Half | \
  35                                 SUPPORTED_1000baseT_Full)
  36
  37#define PHY_BASIC_FEATURES      (PHY_10BT_FEATURES | \
  38                                 PHY_100BT_FEATURES | \
  39                                 PHY_DEFAULT_FEATURES)
  40
  41#define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
  42                                 PHY_1000BT_FEATURES)
  43
  44#define PHY_10G_FEATURES        (PHY_GBIT_FEATURES | \
  45                                SUPPORTED_10000baseT_Full)
  46
  47#ifndef PHY_ANEG_TIMEOUT
  48#define PHY_ANEG_TIMEOUT        4000
  49#endif
  50
  51
  52typedef enum {
  53        PHY_INTERFACE_MODE_MII,
  54        PHY_INTERFACE_MODE_GMII,
  55        PHY_INTERFACE_MODE_SGMII,
  56        PHY_INTERFACE_MODE_SGMII_2500,
  57        PHY_INTERFACE_MODE_QSGMII,
  58        PHY_INTERFACE_MODE_TBI,
  59        PHY_INTERFACE_MODE_RMII,
  60        PHY_INTERFACE_MODE_RGMII,
  61        PHY_INTERFACE_MODE_RGMII_ID,
  62        PHY_INTERFACE_MODE_RGMII_RXID,
  63        PHY_INTERFACE_MODE_RGMII_TXID,
  64        PHY_INTERFACE_MODE_RTBI,
  65        PHY_INTERFACE_MODE_XGMII,
  66        PHY_INTERFACE_MODE_XAUI,
  67        PHY_INTERFACE_MODE_RXAUI,
  68        PHY_INTERFACE_MODE_SFI,
  69        PHY_INTERFACE_MODE_NONE,        /* Must be last */
  70
  71        PHY_INTERFACE_MODE_COUNT,
  72} phy_interface_t;
  73
  74static const char *phy_interface_strings[] = {
  75        [PHY_INTERFACE_MODE_MII]                = "mii",
  76        [PHY_INTERFACE_MODE_GMII]               = "gmii",
  77        [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
  78        [PHY_INTERFACE_MODE_SGMII_2500]         = "sgmii-2500",
  79        [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
  80        [PHY_INTERFACE_MODE_TBI]                = "tbi",
  81        [PHY_INTERFACE_MODE_RMII]               = "rmii",
  82        [PHY_INTERFACE_MODE_RGMII]              = "rgmii",
  83        [PHY_INTERFACE_MODE_RGMII_ID]           = "rgmii-id",
  84        [PHY_INTERFACE_MODE_RGMII_RXID]         = "rgmii-rxid",
  85        [PHY_INTERFACE_MODE_RGMII_TXID]         = "rgmii-txid",
  86        [PHY_INTERFACE_MODE_RTBI]               = "rtbi",
  87        [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
  88        [PHY_INTERFACE_MODE_XAUI]               = "xaui",
  89        [PHY_INTERFACE_MODE_RXAUI]              = "rxaui",
  90        [PHY_INTERFACE_MODE_SFI]                = "sfi",
  91        [PHY_INTERFACE_MODE_NONE]               = "",
  92};
  93
  94static inline const char *phy_string_for_interface(phy_interface_t i)
  95{
  96        /* Default to unknown */
  97        if (i > PHY_INTERFACE_MODE_NONE)
  98                i = PHY_INTERFACE_MODE_NONE;
  99
 100        return phy_interface_strings[i];
 101}
 102
 103
 104struct phy_device;
 105
 106#define MDIO_NAME_LEN 32
 107
 108struct mii_dev {
 109        struct list_head link;
 110        char name[MDIO_NAME_LEN];
 111        void *priv;
 112        int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
 113        int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
 114                        u16 val);
 115        int (*reset)(struct mii_dev *bus);
 116        struct phy_device *phymap[PHY_MAX_ADDR];
 117        u32 phy_mask;
 118};
 119
 120/* struct phy_driver: a structure which defines PHY behavior
 121 *
 122 * uid will contain a number which represents the PHY.  During
 123 * startup, the driver will poll the PHY to find out what its
 124 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 125 * gotten from the PHY will be masked to
 126 * discard any bits which may change based on revision numbers
 127 * unimportant to functionality
 128 *
 129 */
 130struct phy_driver {
 131        char *name;
 132        unsigned int uid;
 133        unsigned int mask;
 134        unsigned int mmds;
 135
 136        u32 features;
 137
 138        /* Called to do any driver startup necessities */
 139        /* Will be called during phy_connect */
 140        int (*probe)(struct phy_device *phydev);
 141
 142        /* Called to configure the PHY, and modify the controller
 143         * based on the results.  Should be called after phy_connect */
 144        int (*config)(struct phy_device *phydev);
 145
 146        /* Called when starting up the controller */
 147        int (*startup)(struct phy_device *phydev);
 148
 149        /* Called when bringing down the controller */
 150        int (*shutdown)(struct phy_device *phydev);
 151
 152        int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
 153        int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
 154                        u16 val);
 155        struct list_head list;
 156};
 157
 158struct phy_device {
 159        /* Information about the PHY type */
 160        /* And management functions */
 161        struct mii_dev *bus;
 162        struct phy_driver *drv;
 163        void *priv;
 164
 165#ifdef CONFIG_DM_ETH
 166        struct udevice *dev;
 167#else
 168        struct eth_device *dev;
 169#endif
 170
 171        /* forced speed & duplex (no autoneg)
 172         * partner speed & duplex & pause (autoneg)
 173         */
 174        int speed;
 175        int duplex;
 176
 177        /* The most recently read link state */
 178        int link;
 179        int port;
 180        phy_interface_t interface;
 181
 182        u32 advertising;
 183        u32 supported;
 184        u32 mmds;
 185
 186        int autoneg;
 187        int addr;
 188        int pause;
 189        int asym_pause;
 190        u32 phy_id;
 191        u32 flags;
 192};
 193
 194struct fixed_link {
 195        int phy_id;
 196        int duplex;
 197        int link_speed;
 198        int pause;
 199        int asym_pause;
 200};
 201
 202static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 203{
 204        struct mii_dev *bus = phydev->bus;
 205
 206        return bus->read(bus, phydev->addr, devad, regnum);
 207}
 208
 209static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
 210                        u16 val)
 211{
 212        struct mii_dev *bus = phydev->bus;
 213
 214        return bus->write(bus, phydev->addr, devad, regnum, val);
 215}
 216
 217#ifdef CONFIG_PHYLIB_10G
 218extern struct phy_driver gen10g_driver;
 219
 220/* For now, XGMII is the only 10G interface */
 221static inline int is_10g_interface(phy_interface_t interface)
 222{
 223        return interface == PHY_INTERFACE_MODE_XGMII;
 224}
 225
 226#endif
 227
 228int phy_init(void);
 229int phy_reset(struct phy_device *phydev);
 230struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
 231                phy_interface_t interface);
 232#ifdef CONFIG_DM_ETH
 233void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
 234struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 235                                struct udevice *dev,
 236                                phy_interface_t interface);
 237#else
 238void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 239struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 240                                struct eth_device *dev,
 241                                phy_interface_t interface);
 242#endif
 243int phy_startup(struct phy_device *phydev);
 244int phy_config(struct phy_device *phydev);
 245int phy_shutdown(struct phy_device *phydev);
 246int phy_register(struct phy_driver *drv);
 247int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 248int genphy_config_aneg(struct phy_device *phydev);
 249int genphy_restart_aneg(struct phy_device *phydev);
 250int genphy_update_link(struct phy_device *phydev);
 251int genphy_parse_link(struct phy_device *phydev);
 252int genphy_config(struct phy_device *phydev);
 253int genphy_startup(struct phy_device *phydev);
 254int genphy_shutdown(struct phy_device *phydev);
 255int gen10g_config(struct phy_device *phydev);
 256int gen10g_startup(struct phy_device *phydev);
 257int gen10g_shutdown(struct phy_device *phydev);
 258int gen10g_discover_mmds(struct phy_device *phydev);
 259
 260int phy_mv88e61xx_init(void);
 261int phy_aquantia_init(void);
 262int phy_atheros_init(void);
 263int phy_broadcom_init(void);
 264int phy_cortina_init(void);
 265int phy_davicom_init(void);
 266int phy_et1011c_init(void);
 267int phy_lxt_init(void);
 268int phy_marvell_init(void);
 269int phy_micrel_ksz8xxx_init(void);
 270int phy_micrel_ksz90x1_init(void);
 271int phy_meson_gxl_init(void);
 272int phy_natsemi_init(void);
 273int phy_realtek_init(void);
 274int phy_smsc_init(void);
 275int phy_teranetics_init(void);
 276int phy_ti_init(void);
 277int phy_vitesse_init(void);
 278int phy_xilinx_init(void);
 279int phy_mscc_init(void);
 280int phy_fixed_init(void);
 281
 282int board_phy_config(struct phy_device *phydev);
 283int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
 284
 285/**
 286 * phy_get_interface_by_name() - Look up a PHY interface name
 287 *
 288 * @str:        PHY interface name, e.g. "mii"
 289 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 290 */
 291int phy_get_interface_by_name(const char *str);
 292
 293/**
 294 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 295 * is RGMII (all variants)
 296 * @phydev: the phy_device struct
 297 */
 298static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 299{
 300        return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
 301                phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 302}
 303
 304/**
 305 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 306 * is SGMII (all variants)
 307 * @phydev: the phy_device struct
 308 */
 309static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 310{
 311        return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
 312                phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
 313}
 314
 315/* PHY UIDs for various PHYs that are referenced in external code */
 316#define PHY_UID_CS4340  0x13e51002
 317#define PHY_UID_TN2020  0x00a19410
 318
 319#endif
 320