1
2
3
4
5
6
7
8
9
10#ifndef __SDHCI_HW_H
11#define __SDHCI_HW_H
12
13#include <asm/io.h>
14#include <mmc.h>
15#include <asm/gpio.h>
16
17
18
19
20
21#define SDHCI_DMA_ADDRESS 0x00
22
23#define SDHCI_BLOCK_SIZE 0x04
24#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
25
26#define SDHCI_BLOCK_COUNT 0x06
27
28#define SDHCI_ARGUMENT 0x08
29
30#define SDHCI_TRANSFER_MODE 0x0C
31#define SDHCI_TRNS_DMA BIT(0)
32#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
33#define SDHCI_TRNS_ACMD12 BIT(2)
34#define SDHCI_TRNS_READ BIT(4)
35#define SDHCI_TRNS_MULTI BIT(5)
36
37#define SDHCI_COMMAND 0x0E
38#define SDHCI_CMD_RESP_MASK 0x03
39#define SDHCI_CMD_CRC 0x08
40#define SDHCI_CMD_INDEX 0x10
41#define SDHCI_CMD_DATA 0x20
42#define SDHCI_CMD_ABORTCMD 0xC0
43
44#define SDHCI_CMD_RESP_NONE 0x00
45#define SDHCI_CMD_RESP_LONG 0x01
46#define SDHCI_CMD_RESP_SHORT 0x02
47#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
48
49#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
50#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
51
52#define SDHCI_RESPONSE 0x10
53
54#define SDHCI_BUFFER 0x20
55
56#define SDHCI_PRESENT_STATE 0x24
57#define SDHCI_CMD_INHIBIT BIT(0)
58#define SDHCI_DATA_INHIBIT BIT(1)
59#define SDHCI_DOING_WRITE BIT(8)
60#define SDHCI_DOING_READ BIT(9)
61#define SDHCI_SPACE_AVAILABLE BIT(10)
62#define SDHCI_DATA_AVAILABLE BIT(11)
63#define SDHCI_CARD_PRESENT BIT(16)
64#define SDHCI_CARD_STATE_STABLE BIT(17)
65#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
66#define SDHCI_WRITE_PROTECT BIT(19)
67#define SDHCI_DATA_BUSY 0xF00000
68#define SDHCI_CMD_BUSY 0x1000000
69
70#define SDHCI_HOST_CONTROL 0x28
71#define SDHCI_CTRL_LED BIT(0)
72#define SDHCI_CTRL_4BITBUS BIT(1)
73#define SDHCI_CTRL_HISPD BIT(2)
74#define SDHCI_CTRL_DMA_MASK 0x18
75#define SDHCI_CTRL_SDMA 0x00
76#define SDHCI_CTRL_ADMA1 0x08
77#define SDHCI_CTRL_ADMA32 0x10
78#define SDHCI_CTRL_ADMA64 0x18
79#define SDHCI_CTRL_8BITBUS BIT(5)
80#define SDHCI_CTRL_CD_TEST_INS BIT(6)
81#define SDHCI_CTRL_CD_TEST BIT(7)
82
83#define SDHCI_POWER_CONTROL 0x29
84#define SDHCI_POWER_ON 0x01
85#define SDHCI_POWER_180 0x0A
86#define SDHCI_POWER_300 0x0C
87#define SDHCI_POWER_330 0x0E
88
89#define SDHCI_BLOCK_GAP_CONTROL 0x2A
90
91#define SDHCI_WAKE_UP_CONTROL 0x2B
92#define SDHCI_WAKE_ON_INT BIT(0)
93#define SDHCI_WAKE_ON_INSERT BIT(1)
94#define SDHCI_WAKE_ON_REMOVE BIT(2)
95
96#define SDHCI_CLOCK_CONTROL 0x2C
97#define SDHCI_DIVIDER_SHIFT 8
98#define SDHCI_DIVIDER_HI_SHIFT 6
99#define SDHCI_DIV_MASK 0xFF
100#define SDHCI_DIV_MASK_LEN 8
101#define SDHCI_DIV_HI_MASK 0x300
102#define SDHCI_PROG_CLOCK_MODE BIT(5)
103#define SDHCI_CLOCK_CARD_EN BIT(2)
104#define SDHCI_CLOCK_INT_STABLE BIT(1)
105#define SDHCI_CLOCK_INT_EN BIT(0)
106
107#define SDHCI_TIMEOUT_CONTROL 0x2E
108
109#define SDHCI_SOFTWARE_RESET 0x2F
110#define SDHCI_RESET_ALL 0x01
111#define SDHCI_RESET_CMD 0x02
112#define SDHCI_RESET_DATA 0x04
113
114#define SDHCI_INT_STATUS 0x30
115#define SDHCI_INT_ENABLE 0x34
116#define SDHCI_SIGNAL_ENABLE 0x38
117#define SDHCI_INT_RESPONSE BIT(0)
118#define SDHCI_INT_DATA_END BIT(1)
119#define SDHCI_INT_DMA_END BIT(3)
120#define SDHCI_INT_SPACE_AVAIL BIT(4)
121#define SDHCI_INT_DATA_AVAIL BIT(5)
122#define SDHCI_INT_CARD_INSERT BIT(6)
123#define SDHCI_INT_CARD_REMOVE BIT(7)
124#define SDHCI_INT_CARD_INT BIT(8)
125#define SDHCI_INT_ERROR BIT(15)
126#define SDHCI_INT_TIMEOUT BIT(16)
127#define SDHCI_INT_CRC BIT(17)
128#define SDHCI_INT_END_BIT BIT(18)
129#define SDHCI_INT_INDEX BIT(19)
130#define SDHCI_INT_DATA_TIMEOUT BIT(20)
131#define SDHCI_INT_DATA_CRC BIT(21)
132#define SDHCI_INT_DATA_END_BIT BIT(22)
133#define SDHCI_INT_BUS_POWER BIT(23)
134#define SDHCI_INT_ACMD12ERR BIT(24)
135#define SDHCI_INT_ADMA_ERROR BIT(25)
136
137#define SDHCI_INT_NORMAL_MASK 0x00007FFF
138#define SDHCI_INT_ERROR_MASK 0xFFFF8000
139
140#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
141 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
142#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
143 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
144 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
145 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
146#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
147
148#define SDHCI_ACMD12_ERR 0x3C
149
150
151#define SDHCI_HOST_CTRL2 0x3E
152#define SDHCI_CTRL2_MODE_MASK 0x7
153
154#define SDHCI_18V_SIGNAL 0x8
155#define SDHCI_CTRL_EXEC_TUNING 0x0040
156#define SDHCI_CTRL_TUNED_CLK 0x80
157
158#define SDHCI_CAPABILITIES 0x40
159#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
160#define SDHCI_TIMEOUT_CLK_SHIFT 0
161#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
162#define SDHCI_CLOCK_BASE_MASK 0x00003F00
163#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
164#define SDHCI_CLOCK_BASE_SHIFT 8
165#define SDHCI_MAX_BLOCK_MASK 0x00030000
166#define SDHCI_MAX_BLOCK_SHIFT 16
167#define SDHCI_CAN_DO_8BIT BIT(18)
168#define SDHCI_CAN_DO_ADMA2 BIT(19)
169#define SDHCI_CAN_DO_ADMA1 BIT(20)
170#define SDHCI_CAN_DO_HISPD BIT(21)
171#define SDHCI_CAN_DO_SDMA BIT(22)
172#define SDHCI_CAN_VDD_330 BIT(24)
173#define SDHCI_CAN_VDD_300 BIT(25)
174#define SDHCI_CAN_VDD_180 BIT(26)
175#define SDHCI_CAN_64BIT BIT(28)
176
177#define SDHCI_CAPABILITIES_1 0x44
178#define SDHCI_SUPPORT_SDR50 0x00000001
179#define SDHCI_SUPPORT_SDR104 0x00000002
180#define SDHCI_SUPPORT_DDR50 0x00000004
181#define SDHCI_USE_SDR50_TUNING 0x00002000
182#define SDHCI_SUPPORT_HS400 0x80000000
183
184#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
185#define SDHCI_CLOCK_MUL_SHIFT 16
186
187#define SDHCI_MAX_CURRENT 0x48
188
189
190
191#define SDHCI_SET_ACMD12_ERROR 0x50
192#define SDHCI_SET_INT_ERROR 0x52
193
194#define SDHCI_ADMA_ERROR 0x54
195
196
197
198#define SDHCI_ADMA_ADDRESS 0x58
199
200
201
202#define SDHCI_SLOT_INT_STATUS 0xFC
203
204#define SDHCI_HOST_VERSION 0xFE
205#define SDHCI_VENDOR_VER_MASK 0xFF00
206#define SDHCI_VENDOR_VER_SHIFT 8
207#define SDHCI_SPEC_VER_MASK 0x00FF
208#define SDHCI_SPEC_VER_SHIFT 0
209#define SDHCI_SPEC_100 0
210#define SDHCI_SPEC_200 1
211#define SDHCI_SPEC_300 2
212
213#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
214
215
216
217
218
219#define SDHCI_MAX_DIV_SPEC_200 256
220#define SDHCI_MAX_DIV_SPEC_300 2046
221
222
223
224
225#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
226#define SDHCI_QUIRK_REG32_RW (1 << 1)
227#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
228#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
229#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
230#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
231#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
232#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
233#define SDHCI_QUIRK_USE_ACMD12 (1 << 10)
234
235
236struct sdhci_host;
237
238
239
240
241#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
242#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
243struct sdhci_ops {
244#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
245 u32 (*read_l)(struct sdhci_host *host, int reg);
246 u16 (*read_w)(struct sdhci_host *host, int reg);
247 u8 (*read_b)(struct sdhci_host *host, int reg);
248 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
249 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
250 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
251#endif
252 int (*get_cd)(struct sdhci_host *host);
253 void (*set_control_reg)(struct sdhci_host *host);
254 void (*set_ios_post)(struct sdhci_host *host);
255 void (*set_clock)(struct sdhci_host *host, u32 div);
256};
257
258struct sdhci_host {
259 const char *name;
260 void *ioaddr;
261 unsigned int quirks;
262 unsigned int host_caps;
263 unsigned int version;
264 unsigned int max_clk;
265 unsigned int clk_mul;
266 unsigned int clock;
267 struct mmc *mmc;
268 struct sdhci_ops *ops;
269 int index;
270
271 int bus_width;
272 struct gpio_desc pwr_gpio;
273 struct gpio_desc cd_gpio;
274
275 void (*set_control_reg)(struct sdhci_host *host);
276 void (*set_clock)(int dev_index, unsigned int div);
277 int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
278 void (*set_delay)(struct sdhci_host *host);
279 uint voltages;
280
281 struct mmc_config cfg;
282 unsigned int last_cmd;
283};
284
285#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
286
287static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
288{
289 if (unlikely(host->ops->write_l))
290 host->ops->write_l(host, val, reg);
291 else
292 writel(val, host->ioaddr + reg);
293}
294
295static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
296{
297 if (unlikely(host->ops->write_w))
298 host->ops->write_w(host, val, reg);
299 else
300 writew(val, host->ioaddr + reg);
301}
302
303static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
304{
305 if (unlikely(host->ops->write_b))
306 host->ops->write_b(host, val, reg);
307 else
308 writeb(val, host->ioaddr + reg);
309}
310
311static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
312{
313 if (unlikely(host->ops->read_l))
314 return host->ops->read_l(host, reg);
315 else
316 return readl(host->ioaddr + reg);
317}
318
319static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
320{
321 if (unlikely(host->ops->read_w))
322 return host->ops->read_w(host, reg);
323 else
324 return readw(host->ioaddr + reg);
325}
326
327static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
328{
329 if (unlikely(host->ops->read_b))
330 return host->ops->read_b(host, reg);
331 else
332 return readb(host->ioaddr + reg);
333}
334
335#else
336
337static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
338{
339 writel(val, host->ioaddr + reg);
340}
341
342static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
343{
344 writew(val, host->ioaddr + reg);
345}
346
347static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
348{
349 writeb(val, host->ioaddr + reg);
350}
351static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
352{
353 return readl(host->ioaddr + reg);
354}
355
356static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
357{
358 return readw(host->ioaddr + reg);
359}
360
361static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
362{
363 return readb(host->ioaddr + reg);
364}
365#endif
366
367#ifdef CONFIG_BLK
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
401 u32 f_max, u32 f_min);
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
419#else
420
421
422
423
424
425
426
427
428
429
430
431int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
432#endif
433
434#ifdef CONFIG_DM_MMC
435
436int sdhci_probe(struct udevice *dev);
437extern const struct dm_mmc_ops sdhci_ops;
438#else
439#endif
440
441#endif
442