1/* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6#ifndef _ASM_ARCH_TIMER_H 7#define _ASM_ARCH_TIMER_H 8 9/* Each timer has 4 control bits in ctrl1 register. 10 * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, 11 * such that timer X uses bits (4 * X - 4):(4 * X - 1) 12 * If the timer does not support PWM, bit 4 is reserved. 13 */ 14#define AST_TMC_EN (1 << 0) 15#define AST_TMC_1MHZ (1 << 1) 16#define AST_TMC_OVFINTR (1 << 2) 17#define AST_TMC_PWM (1 << 3) 18 19/* Timers are counted from 1 in the datasheet. */ 20#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) 21 22#define AST_TMC_RATE (1000*1000) 23 24#ifndef __ASSEMBLY__ 25 26/* 27 * All timers share control registers, which makes it harder to make them 28 * separate devices. Since only one timer is needed at the moment, making 29 * it this just one device. 30 */ 31 32struct ast_timer_counter { 33 u32 status; 34 u32 reload_val; 35 u32 match1; 36 u32 match2; 37}; 38 39struct ast_timer { 40 struct ast_timer_counter timers1[3]; 41 u32 ctrl1; 42 u32 ctrl2; 43#ifdef CONFIG_ASPEED_AST2500 44 u32 ctrl3; 45 u32 ctrl1_clr; 46#else 47 u32 reserved[2]; 48#endif 49 struct ast_timer_counter timers2[5]; 50}; 51 52#endif /* __ASSEMBLY__ */ 53 54#endif /* _ASM_ARCH_TIMER_H */ 55