LXR uboot/arch/arm/include/asm/arch-mx6/clock.h

   1/*
   2 * (C) Copyright 2009
   3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __ASM_ARCH_CLOCK_H
   9#define __ASM_ARCH_CLOCK_H
  10
  11#include <common.h>
  12
  13#ifdef CONFIG_SYS_MX6_HCLK
  14#define MXC_HCLK        CONFIG_SYS_MX6_HCLK
  15#else
  16#define MXC_HCLK        24000000
  17#endif
  18
  19#ifdef CONFIG_SYS_MX6_CLK32
  20#define MXC_CLK32       CONFIG_SYS_MX6_CLK32
  21#else
  22#define MXC_CLK32       32768
  23#endif
  24
  25enum mxc_clock {
  26        MXC_ARM_CLK = 0,
  27        MXC_PER_CLK,
  28        MXC_AHB_CLK,
  29        MXC_IPG_CLK,
  30        MXC_IPG_PERCLK,
  31        MXC_UART_CLK,
  32        MXC_CSPI_CLK,
  33        MXC_AXI_CLK,
  34        MXC_EMI_SLOW_CLK,
  35        MXC_DDR_CLK,
  36        MXC_ESDHC_CLK,
  37        MXC_ESDHC2_CLK,
  38        MXC_ESDHC3_CLK,
  39        MXC_ESDHC4_CLK,
  40        MXC_SATA_CLK,
  41        MXC_NFC_CLK,
  42        MXC_I2C_CLK,
  43};
  44
  45enum ldb_di_clock {
  46        MXC_PLL5_CLK = 0,
  47        MXC_PLL2_PFD0_CLK,
  48        MXC_PLL2_PFD2_CLK,
  49        MXC_MMDC_CH1_CLK,
  50        MXC_PLL3_SW_CLK,
  51};
  52
  53enum enet_freq {
  54        ENET_25MHZ,
  55        ENET_50MHZ,
  56        ENET_100MHZ,
  57        ENET_125MHZ,
  58};
  59
  60u32 imx_get_uartclk(void);
  61u32 imx_get_fecclk(void);
  62unsigned int mxc_get_clock(enum mxc_clock clk);
  63void setup_gpmi_io_clk(u32 cfg);
  64void hab_caam_clock_enable(unsigned char enable);
  65void enable_ocotp_clk(unsigned char enable);
  66void enable_usboh3_clk(unsigned char enable);
  67void enable_uart_clk(unsigned char enable);
  68int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
  69int enable_sata_clock(void);
  70void disable_sata_clock(void);
  71int enable_pcie_clock(void);
  72int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  73int enable_spi_clk(unsigned char enable, unsigned spi_num);
  74void enable_ipu_clock(void);
  75int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
  76void enable_enet_clk(unsigned char enable);
  77int enable_lcdif_clock(u32 base_addr, bool enable);
  78void enable_qspi_clk(int qspi_num);
  79void enable_thermal_clk(void);
  80void mxs_set_lcdclk(u32 base_addr, u32 freq);
  81void select_ldb_di_clock_source(enum ldb_di_clock clk);
  82void enable_eim_clk(unsigned char enable);
  83int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
  84#endif /* __ASM_ARCH_CLOCK_H */
  85