LXR uboot/arch/arm/mach-omap2/omap-cache.c

   1/*
   2 *
   3 * Common functions for OMAP4/5 based boards
   4 *
   5 * (C) Copyright 2010
   6 * Texas Instruments, <www.ti.com>
   7 *
   8 * Author :
   9 *      Aneesh V        <aneesh@ti.com>
  10 *      Steve Sakoman   <steve@sakoman.com>
  11 *
  12 * SPDX-License-Identifier:     GPL-2.0+
  13 */
  14
  15#include <common.h>
  16#include <asm/cache.h>
  17
  18DECLARE_GLOBAL_DATA_PTR;
  19
  20/*
  21 * Without LPAE short descriptors are used
  22 * Set C - Cache Bit3
  23 * Set B - Buffer Bit2
  24 * The last 2 bits set to 0b10
  25 * Do Not set XN bit4
  26 * So value is 0xe
  27 *
  28 * With LPAE cache configuration happens via MAIR0 register
  29 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
  30 * 0xFF maps to Cache writeback with Read and Write Allocate set
  31 * The bits[1:0] should have the value 0b01 for the first level
  32 * descriptor.
  33 * So the value is 0xd
  34 */
  35
  36#ifdef CONFIG_ARMV7_LPAE
  37#define ARMV7_DCACHE_POLICY     DCACHE_WRITEALLOC
  38#else
  39#define ARMV7_DCACHE_POLICY     DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
  40#endif
  41
  42#define ARMV7_DOMAIN_CLIENT     1
  43#define ARMV7_DOMAIN_MASK       (0x3 << 0)
  44
  45void enable_caches(void)
  46{
  47        /* Enable D-cache. I-cache is already enabled in start.S */
  48        dcache_enable();
  49}
  50
  51void dram_bank_mmu_setup(int bank)
  52{
  53        bd_t *bd = gd->bd;
  54        int     i;
  55
  56        u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  57        u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
  58        u32 end = start + size;
  59
  60        debug("%s: bank: %d\n", __func__, bank);
  61        for (i = start; i < end; i++)
  62                set_section_dcache(i, ARMV7_DCACHE_POLICY);
  63}
  64
  65void arm_init_domains(void)
  66{
  67        u32 reg;
  68
  69        reg = get_dacr();
  70        /*
  71        * Set DOMAIN to client access so that all permissions
  72        * set in pagetables are validated by the mmu.
  73        */
  74        reg &= ~ARMV7_DOMAIN_MASK;
  75        reg |= ARMV7_DOMAIN_CLIENT;
  76        set_dacr(reg);
  77}
  78