uboot/board/congatec/cgtqmx6eval/cgtqmx6eval.c
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   1/*
   2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3 * Based on mx6qsabrelite.c file
   4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5 * Leo Sartre, <lsartre@adeneo-embedded.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <asm/io.h>
  12#include <asm/arch/clock.h>
  13#include <asm/arch/imx-regs.h>
  14#include <asm/arch/iomux.h>
  15#include <asm/arch/mx6-pins.h>
  16#include <asm/gpio.h>
  17#include <asm/mach-imx/iomux-v3.h>
  18#include <asm/mach-imx/sata.h>
  19#include <asm/mach-imx/boot_mode.h>
  20#include <asm/mach-imx/mxc_i2c.h>
  21#include <asm/arch/sys_proto.h>
  22#include <asm/arch/mxc_hdmi.h>
  23#include <asm/arch/crm_regs.h>
  24#include <mmc.h>
  25#include <fsl_esdhc.h>
  26#include <i2c.h>
  27#include <input.h>
  28#include <power/pmic.h>
  29#include <power/pfuze100_pmic.h>
  30#include <linux/fb.h>
  31#include <ipu_pixfmt.h>
  32#include <malloc.h>
  33#include <miiphy.h>
  34#include <netdev.h>
  35#include <micrel.h>
  36#include <spi_flash.h>
  37#include <spi.h>
  38
  39DECLARE_GLOBAL_DATA_PTR;
  40
  41#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  42        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  45        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  48        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  49        PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  50        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  51
  52#define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  53        PAD_CTL_SPEED_MED |             \
  54        PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  55
  56#define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  57
  58
  59#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  60        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  61        PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  62
  63int dram_init(void)
  64{
  65        gd->ram_size = imx_ddr_size();
  66
  67        return 0;
  68}
  69
  70static iomux_v3_cfg_t const uart2_pads[] = {
  71        IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  72        IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  73};
  74
  75#ifndef CONFIG_SPL_BUILD
  76static iomux_v3_cfg_t const usdhc2_pads[] = {
  77        IOMUX_PADS(PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78        IOMUX_PADS(PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79        IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80        IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  81        IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82        IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83        IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84};
  85
  86static iomux_v3_cfg_t const usdhc3_pads[] = {
  87        IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88        IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89        IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90        IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91        IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92        IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93        IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94        IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95        IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96        IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  97        IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  98};
  99#endif
 100
 101static iomux_v3_cfg_t const usdhc4_pads[] = {
 102        IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 103        IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 104        IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 105        IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 106        IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 107        IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108        IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109        IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 110        IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 111        IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 112        IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 113};
 114
 115static iomux_v3_cfg_t const usb_otg_pads[] = {
 116        IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
 117        IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 118};
 119
 120static iomux_v3_cfg_t enet_pads_ksz9031[] = {
 121        IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 122        IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 123        IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 124        IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 125        IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 126        IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 127        IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 128        IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 129        IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 130        IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 131        IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 132        IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 133        IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 134        IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 135        IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 136};
 137
 138static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
 139        IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 140        IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 141        IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 142        IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 143        IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 144        IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 145};
 146
 147static iomux_v3_cfg_t enet_pads_ar8035[] = {
 148        IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 149        IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 150        IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 151        IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 152        IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 153        IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 154        IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 155        IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 156        IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 157        IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 158        IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 159        IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 160        IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 161        IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 162        IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 163};
 164
 165static iomux_v3_cfg_t const ecspi1_pads[] = {
 166        IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 167        IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 168        IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 169        IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 170};
 171
 172#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 173struct i2c_pads_info mx6q_i2c_pad_info1 = {
 174        .scl = {
 175                .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 176                .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 177                .gp = IMX_GPIO_NR(4, 12)
 178        },
 179        .sda = {
 180                .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 181                .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 182                .gp = IMX_GPIO_NR(4, 13)
 183        }
 184};
 185
 186struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 187        .scl = {
 188                .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 189                .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 190                .gp = IMX_GPIO_NR(4, 12)
 191        },
 192        .sda = {
 193                .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 194                .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 195                .gp = IMX_GPIO_NR(4, 13)
 196        }
 197};
 198
 199#define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 200
 201struct interface_level {
 202        char *name;
 203        uchar value;
 204};
 205
 206static struct interface_level mipi_levels[] = {
 207        {"0V0", 0x00},
 208        {"2V5", 0x17},
 209};
 210
 211/* setup board specific PMIC */
 212int power_init_board(void)
 213{
 214        struct pmic *p;
 215        u32 id1, id2, i;
 216        int ret;
 217        char const *lv_mipi;
 218
 219        /* configure I2C multiplexer */
 220        gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 221
 222        power_pfuze100_init(I2C_PMIC);
 223        p = pmic_get("PFUZE100");
 224        if (!p)
 225                return -EINVAL;
 226
 227        ret = pmic_probe(p);
 228        if (ret)
 229                return ret;
 230
 231        pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 232        pmic_reg_read(p, PFUZE100_REVID, &id2);
 233        printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 234
 235        if (id2 >= 0x20)
 236                return 0;
 237
 238        /* set level of MIPI if specified */
 239        lv_mipi = env_get("lv_mipi");
 240        if (lv_mipi)
 241                return 0;
 242
 243        for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 244                if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 245                        printf("set MIPI level %s\n", mipi_levels[i].name);
 246                        ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 247                                             mipi_levels[i].value);
 248                        if (ret)
 249                                return ret;
 250                }
 251        }
 252
 253        return 0;
 254}
 255
 256int board_eth_init(bd_t *bis)
 257{
 258        struct phy_device *phydev;
 259        struct mii_dev *bus;
 260        unsigned short id1, id2;
 261        int ret;
 262
 263        /* check whether KSZ9031 or AR8035 has to be configured */
 264        SETUP_IOMUX_PADS(enet_pads_ar8035);
 265
 266        /* phy reset */
 267        gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 268        udelay(2000);
 269        gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 270        udelay(500);
 271
 272        bus = fec_get_miibus(IMX_FEC_BASE, -1);
 273        if (!bus)
 274                return -EINVAL;
 275        phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 276        if (!phydev) {
 277                printf("Error: phy device not found.\n");
 278                ret = -ENODEV;
 279                goto free_bus;
 280        }
 281
 282        /* get the PHY id */
 283        id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
 284        id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
 285
 286        if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
 287                /* re-configure for Micrel KSZ9031 */
 288                printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
 289                       phydev->addr);
 290
 291                /* phy reset: gpio3-23 */
 292                gpio_set_value(IMX_GPIO_NR(3, 23), 0);
 293                gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
 294                gpio_set_value(IMX_GPIO_NR(6, 25), 1);
 295                gpio_set_value(IMX_GPIO_NR(6, 27), 1);
 296                gpio_set_value(IMX_GPIO_NR(6, 28), 1);
 297                gpio_set_value(IMX_GPIO_NR(6, 29), 1);
 298                SETUP_IOMUX_PADS(enet_pads_ksz9031);
 299                gpio_set_value(IMX_GPIO_NR(6, 24), 1);
 300                udelay(500);
 301                gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 302                SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
 303        } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
 304                /* configure Atheros AR8035 - actually nothing to do */
 305                printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
 306                       phydev->addr);
 307        } else {
 308                printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
 309                ret = -EINVAL;
 310                goto free_phydev;
 311        }
 312
 313        ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 314        if (ret)
 315                goto free_phydev;
 316
 317        return 0;
 318
 319free_phydev:
 320        free(phydev);
 321free_bus:
 322        free(bus);
 323        return ret;
 324}
 325
 326int mx6_rgmii_rework(struct phy_device *phydev)
 327{
 328        unsigned short id1, id2;
 329        unsigned short val;
 330
 331        /* check whether KSZ9031 or AR8035 has to be configured */
 332        id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
 333        id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
 334
 335        if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
 336                /* finalize phy configuration for Micrel KSZ9031 */
 337                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 338                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
 339                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 340                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
 341
 342                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 343                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
 344                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 345                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
 346
 347                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 348                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
 349                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 350                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
 351
 352                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 353                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
 354                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 355                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
 356
 357                /* fix KSZ9031 link up issue */
 358                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
 359                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
 360                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
 361                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
 362                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
 363                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
 364                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
 365                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
 366        }
 367
 368        if ((id1 == 0x004d) && (id2 == 0xd072)) {
 369                /* enable AR8035 ouput a 125MHz clk from CLK_25M */
 370                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
 371                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
 372                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
 373                val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
 374                val &= 0xfe63;
 375                val |= 0x18;
 376                phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
 377
 378                /* introduce tx clock delay */
 379                phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 380                val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 381                val |= 0x0100;
 382                phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 383
 384                /* disable hibernation */
 385                phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
 386                val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 387                phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
 388        }
 389        return 0;
 390}
 391
 392int board_phy_config(struct phy_device *phydev)
 393{
 394        mx6_rgmii_rework(phydev);
 395
 396        if (phydev->drv->config)
 397                phydev->drv->config(phydev);
 398
 399        return 0;
 400}
 401 
 402static void setup_iomux_uart(void)
 403{
 404        SETUP_IOMUX_PADS(uart2_pads);
 405}
 406
 407#ifdef CONFIG_MXC_SPI
 408static void setup_spi(void)
 409{
 410        SETUP_IOMUX_PADS(ecspi1_pads);
 411        gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
 412}
 413#endif
 414
 415#ifdef CONFIG_FSL_ESDHC
 416static struct fsl_esdhc_cfg usdhc_cfg[] = {
 417        {USDHC2_BASE_ADDR},
 418        {USDHC3_BASE_ADDR},
 419        {USDHC4_BASE_ADDR},
 420};
 421
 422int board_mmc_getcd(struct mmc *mmc)
 423{
 424        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 425        int ret = 0;
 426
 427        switch (cfg->esdhc_base) {
 428        case USDHC2_BASE_ADDR:
 429                gpio_direction_input(IMX_GPIO_NR(1, 4));
 430                ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 431                break;
 432        case USDHC3_BASE_ADDR:
 433                ret = 1;        /* eMMC is always present */
 434                break;
 435        case USDHC4_BASE_ADDR:
 436                gpio_direction_input(IMX_GPIO_NR(2, 6));
 437                ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 438                break;
 439        default:
 440                printf("Bad USDHC interface\n");
 441        }
 442
 443        return ret;
 444}
 445
 446int board_mmc_init(bd_t *bis)
 447{
 448#ifndef CONFIG_SPL_BUILD
 449        s32 status = 0;
 450        int i;
 451
 452        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 453        usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 454        usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 455
 456        SETUP_IOMUX_PADS(usdhc2_pads);
 457        SETUP_IOMUX_PADS(usdhc3_pads);
 458        SETUP_IOMUX_PADS(usdhc4_pads);
 459
 460        for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 461                status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 462                if (status)
 463                        return status;
 464        }
 465
 466        return 0;
 467#else
 468        SETUP_IOMUX_PADS(usdhc4_pads);
 469        usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 470        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 471        gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 472
 473        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 474#endif
 475}
 476#endif
 477
 478int board_ehci_hcd_init(int port)
 479{
 480        switch (port) {
 481        case 0:
 482                SETUP_IOMUX_PADS(usb_otg_pads);
 483                /*
 484                 * set daisy chain for otg_pin_id on 6q.
 485                 * for 6dl, this bit is reserved
 486                 */
 487                imx_iomux_set_gpr_register(1, 13, 1, 1);
 488                break;
 489        case 1:
 490                /* nothing to do */
 491                break;
 492        default:
 493                printf("Invalid USB port: %d\n", port);
 494                return -EINVAL;
 495        }
 496
 497        return 0;
 498}
 499
 500int board_ehci_power(int port, int on)
 501{
 502        switch (port) {
 503        case 0:
 504                break;
 505        case 1:
 506                gpio_direction_output(IMX_GPIO_NR(5, 5), on);
 507                break;
 508        default:
 509                printf("Invalid USB port: %d\n", port);
 510                return -EINVAL;
 511        }
 512
 513        return 0;
 514}
 515
 516struct display_info_t {
 517        int bus;
 518        int addr;
 519        int pixfmt;
 520        int (*detect)(struct display_info_t const *dev);
 521        void (*enable)(struct display_info_t const *dev);
 522        struct fb_videomode mode;
 523};
 524
 525static void disable_lvds(struct display_info_t const *dev)
 526{
 527        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 528
 529        clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 530                     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 531}
 532
 533static void do_enable_hdmi(struct display_info_t const *dev)
 534{
 535        disable_lvds(dev);
 536        imx_enable_hdmi_phy();
 537}
 538
 539static struct display_info_t const displays[] = {
 540{
 541        .bus = -1,
 542        .addr = 0,
 543        .pixfmt = IPU_PIX_FMT_RGB666,
 544        .detect = NULL,
 545        .enable = NULL,
 546        .mode = {
 547                .name =
 548                "Hannstar-XGA",
 549                .refresh = 60,
 550                .xres = 1024,
 551                .yres = 768,
 552                .pixclock = 15385,
 553                .left_margin = 220,
 554                .right_margin = 40,
 555                .upper_margin = 21,
 556                .lower_margin = 7,
 557                .hsync_len = 60,
 558                .vsync_len = 10,
 559                .sync = FB_SYNC_EXT,
 560                .vmode = FB_VMODE_NONINTERLACED } },
 561{
 562        .bus = -1,
 563        .addr = 0,
 564        .pixfmt = IPU_PIX_FMT_RGB24,
 565        .detect = NULL,
 566        .enable = do_enable_hdmi,
 567        .mode = {
 568                .name = "HDMI",
 569                .refresh = 60,
 570                .xres = 1024,
 571                .yres = 768,
 572                .pixclock = 15385,
 573                .left_margin = 220,
 574                .right_margin = 40,
 575                .upper_margin = 21,
 576                .lower_margin = 7,
 577                .hsync_len = 60,
 578                .vsync_len = 10,
 579                .sync = FB_SYNC_EXT,
 580                .vmode = FB_VMODE_NONINTERLACED } }
 581};
 582
 583int board_video_skip(void)
 584{
 585        int i;
 586        int ret;
 587        char const *panel = env_get("panel");
 588        if (!panel) {
 589                for (i = 0; i < ARRAY_SIZE(displays); i++) {
 590                        struct display_info_t const *dev = displays + i;
 591                        if (dev->detect && dev->detect(dev)) {
 592                                panel = dev->mode.name;
 593                                printf("auto-detected panel %s\n", panel);
 594                                break;
 595                        }
 596                }
 597                if (!panel) {
 598                        panel = displays[0].mode.name;
 599                        printf("No panel detected: default to %s\n", panel);
 600                        i = 0;
 601                }
 602        } else {
 603                for (i = 0; i < ARRAY_SIZE(displays); i++) {
 604                        if (!strcmp(panel, displays[i].mode.name))
 605                                break;
 606                }
 607        }
 608        if (i < ARRAY_SIZE(displays)) {
 609                ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
 610                if (!ret) {
 611                        if (displays[i].enable)
 612                                displays[i].enable(displays + i);
 613                        printf("Display: %s (%ux%u)\n",
 614                               displays[i].mode.name, displays[i].mode.xres,
 615                               displays[i].mode.yres);
 616                } else
 617                        printf("LCD %s cannot be configured: %d\n",
 618                               displays[i].mode.name, ret);
 619        } else {
 620                printf("unsupported panel %s\n", panel);
 621                return -EINVAL;
 622        }
 623
 624        return 0;
 625}
 626
 627static void setup_display(void)
 628{
 629        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 630        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 631        int reg;
 632
 633        enable_ipu_clock();
 634        imx_setup_hdmi();
 635
 636        /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 637        setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
 638                     MXC_CCM_CCGR3_LDB_DI1_MASK);
 639
 640        /* set LDB0, LDB1 clk select to 011/011 */
 641        reg = readl(&mxc_ccm->cs2cdr);
 642        reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 643                 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 644        reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 645                (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 646        writel(reg, &mxc_ccm->cs2cdr);
 647
 648        setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
 649                     MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
 650
 651        setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
 652                     MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
 653                     CHSCCDR_CLK_SEL_LDB_DI0 <<
 654                     MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 655
 656        reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 657                | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 658                | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 659                | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 660                | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 661                | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 662                | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 663                | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 664                | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 665        writel(reg, &iomux->gpr[2]);
 666
 667        reg = readl(&iomux->gpr[3]);
 668        reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 669                       IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
 670                (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 671                 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 672        writel(reg, &iomux->gpr[3]);
 673}
 674
 675/*
 676 * Do not overwrite the console
 677 * Use always serial for U-Boot console
 678 */
 679int overwrite_console(void)
 680{
 681        return 1;
 682}
 683
 684int board_early_init_f(void)
 685{
 686        setup_iomux_uart();
 687#ifdef CONFIG_MXC_SPI
 688        setup_spi();
 689#endif
 690        return 0;
 691}
 692
 693int board_init(void)
 694{
 695        /* address of boot parameters */
 696        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 697
 698
 699        if (is_mx6dq())
 700                setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 701        else
 702                setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 703
 704        setup_display();
 705
 706#ifdef CONFIG_SATA
 707        setup_sata();
 708#endif
 709
 710        return 0;
 711}
 712
 713int checkboard(void)
 714{
 715        char *type = "unknown";
 716
 717        if (is_cpu_type(MXC_CPU_MX6Q))
 718                type = "Quad";
 719        else if (is_cpu_type(MXC_CPU_MX6D))
 720                type = "Dual";
 721        else if (is_cpu_type(MXC_CPU_MX6DL))
 722                type = "Dual-Lite";
 723        else if (is_cpu_type(MXC_CPU_MX6SOLO))
 724                type = "Solo";
 725
 726        printf("Board: conga-QMX6 %s\n", type);
 727
 728        return 0;
 729}
 730
 731#ifdef CONFIG_MXC_SPI
 732int board_spi_cs_gpio(unsigned bus, unsigned cs)
 733{
 734        return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
 735}
 736#endif
 737
 738#ifdef CONFIG_CMD_BMODE
 739static const struct boot_mode board_boot_modes[] = {
 740        /* 4 bit bus width */
 741        {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 742        {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 743        {NULL,          0},
 744};
 745#endif
 746
 747int misc_init_r(void)
 748{
 749#ifdef CONFIG_CMD_BMODE
 750        add_board_boot_modes(board_boot_modes);
 751#endif
 752        return 0;
 753}
 754
 755int board_late_init(void)
 756{
 757#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 758        if (is_mx6dq())
 759                env_set("board_rev", "MX6Q");
 760        else
 761                env_set("board_rev", "MX6DL");
 762#endif
 763
 764        return 0;
 765}
 766
 767#ifdef CONFIG_SPL_BUILD
 768#include <asm/arch/mx6-ddr.h>
 769#include <spl.h>
 770#include <libfdt.h>
 771#include <spi_flash.h>
 772#include <spi.h>
 773
 774const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 775        .dram_sdclk_0 =  0x00000030,
 776        .dram_sdclk_1 =  0x00000030,
 777        .dram_cas =  0x00000030,
 778        .dram_ras =  0x00000030,
 779        .dram_reset =  0x00000030,
 780        .dram_sdcke0 =  0x00003000,
 781        .dram_sdcke1 =  0x00003000,
 782        .dram_sdba2 =  0x00000000,
 783        .dram_sdodt0 =  0x00000030,
 784        .dram_sdodt1 =  0x00000030,
 785        .dram_sdqs0 =  0x00000030,
 786        .dram_sdqs1 =  0x00000030,
 787        .dram_sdqs2 =  0x00000030,
 788        .dram_sdqs3 =  0x00000030,
 789        .dram_sdqs4 =  0x00000030,
 790        .dram_sdqs5 =  0x00000030,
 791        .dram_sdqs6 =  0x00000030,
 792        .dram_sdqs7 =  0x00000030,
 793        .dram_dqm0 =  0x00000030,
 794        .dram_dqm1 =  0x00000030,
 795        .dram_dqm2 =  0x00000030,
 796        .dram_dqm3 =  0x00000030,
 797        .dram_dqm4 =  0x00000030,
 798        .dram_dqm5 =  0x00000030,
 799        .dram_dqm6 =  0x00000030,
 800        .dram_dqm7 =  0x00000030,
 801};
 802
 803static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 804        .dram_sdclk_0 = 0x00000030,
 805        .dram_sdclk_1 = 0x00000030,
 806        .dram_cas =     0x00000030,
 807        .dram_ras =     0x00000030,
 808        .dram_reset =   0x00000030,
 809        .dram_sdcke0 =  0x00003000,
 810        .dram_sdcke1 =  0x00003000,
 811        .dram_sdba2 =   0x00000000,
 812        .dram_sdodt0 =  0x00000030,
 813        .dram_sdodt1 =  0x00000030,
 814        .dram_sdqs0 =   0x00000030,
 815        .dram_sdqs1 =   0x00000030,
 816        .dram_sdqs2 =   0x00000030,
 817        .dram_sdqs3 =   0x00000030,
 818        .dram_sdqs4 =   0x00000030,
 819        .dram_sdqs5 =   0x00000030,
 820        .dram_sdqs6 =   0x00000030,
 821        .dram_sdqs7 =   0x00000030,
 822        .dram_dqm0 =    0x00000030,
 823        .dram_dqm1 =    0x00000030,
 824        .dram_dqm2 =    0x00000030,
 825        .dram_dqm3 =    0x00000030,
 826        .dram_dqm4 =    0x00000030,
 827        .dram_dqm5 =    0x00000030,
 828        .dram_dqm6 =    0x00000030,
 829        .dram_dqm7 =    0x00000030,
 830};
 831
 832const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 833        .grp_ddr_type =  0x000C0000,
 834        .grp_ddrmode_ctl =  0x00020000,
 835        .grp_ddrpke =  0x00000000,
 836        .grp_addds =  0x00000030,
 837        .grp_ctlds =  0x00000030,
 838        .grp_ddrmode =  0x00020000,
 839        .grp_b0ds =  0x00000030,
 840        .grp_b1ds =  0x00000030,
 841        .grp_b2ds =  0x00000030,
 842        .grp_b3ds =  0x00000030,
 843        .grp_b4ds =  0x00000030,
 844        .grp_b5ds =  0x00000030,
 845        .grp_b6ds =  0x00000030,
 846        .grp_b7ds =  0x00000030,
 847};
 848
 849static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 850        .grp_ddr_type = 0x000c0000,
 851        .grp_ddrmode_ctl = 0x00020000,
 852        .grp_ddrpke = 0x00000000,
 853        .grp_addds = 0x00000030,
 854        .grp_ctlds = 0x00000030,
 855        .grp_ddrmode = 0x00020000,
 856        .grp_b0ds = 0x00000030,
 857        .grp_b1ds = 0x00000030,
 858        .grp_b2ds = 0x00000030,
 859        .grp_b3ds = 0x00000030,
 860        .grp_b4ds = 0x00000030,
 861        .grp_b5ds = 0x00000030,
 862        .grp_b6ds = 0x00000030,
 863        .grp_b7ds = 0x00000030,
 864};
 865
 866const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
 867        .p0_mpwldectrl0 =  0x0016001A,
 868        .p0_mpwldectrl1 =  0x0023001C,
 869        .p1_mpwldectrl0 =  0x0028003A,
 870        .p1_mpwldectrl1 =  0x001F002C,
 871        .p0_mpdgctrl0 =  0x43440354,
 872        .p0_mpdgctrl1 =  0x033C033C,
 873        .p1_mpdgctrl0 =  0x43300368,
 874        .p1_mpdgctrl1 =  0x03500330,
 875        .p0_mprddlctl =  0x3228242E,
 876        .p1_mprddlctl =  0x2C2C2636,
 877        .p0_mpwrdlctl =  0x36323A38,
 878        .p1_mpwrdlctl =  0x42324440,
 879};
 880
 881const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 882        .p0_mpwldectrl0 =  0x00080016,
 883        .p0_mpwldectrl1 =  0x001D0016,
 884        .p1_mpwldectrl0 =  0x0018002C,
 885        .p1_mpwldectrl1 =  0x000D001D,
 886        .p0_mpdgctrl0 =    0x43200334,
 887        .p0_mpdgctrl1 =    0x0320031C,
 888        .p1_mpdgctrl0 =    0x0344034C,
 889        .p1_mpdgctrl1 =    0x03380314,
 890        .p0_mprddlctl =    0x3E36383A,
 891        .p1_mprddlctl =    0x38363240,
 892        .p0_mpwrdlctl =    0x36364238,
 893        .p1_mpwrdlctl =    0x4230423E,
 894};
 895
 896static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
 897        .p0_mpwldectrl0 =  0x00480049,
 898        .p0_mpwldectrl1 =  0x00410044,
 899        .p0_mpdgctrl0 =    0x42480248,
 900        .p0_mpdgctrl1 =    0x023C023C,
 901        .p0_mprddlctl =    0x40424644,
 902        .p0_mpwrdlctl =    0x34323034,
 903};
 904
 905const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
 906        .p0_mpwldectrl0 =  0x0043004B,
 907        .p0_mpwldectrl1 =  0x003A003E,
 908        .p1_mpwldectrl0 =  0x0047004F,
 909        .p1_mpwldectrl1 =  0x004E0061,
 910        .p0_mpdgctrl0 =    0x42500250,
 911        .p0_mpdgctrl1 =    0x0238023C,
 912        .p1_mpdgctrl0 =    0x42640264,
 913        .p1_mpdgctrl1 =    0x02500258,
 914        .p0_mprddlctl =    0x40424846,
 915        .p1_mprddlctl =    0x46484842,
 916        .p0_mpwrdlctl =    0x38382C30,
 917        .p1_mpwrdlctl =    0x34343430,
 918};
 919
 920static struct mx6_ddr3_cfg mem_ddr_2g = {
 921        .mem_speed = 1600,
 922        .density = 2,
 923        .width = 16,
 924        .banks = 8,
 925        .rowaddr = 14,
 926        .coladdr = 10,
 927        .pagesz = 2,
 928        .trcd = 1310,
 929        .trcmin = 4875,
 930        .trasmin = 3500,
 931};
 932
 933static struct mx6_ddr3_cfg mem_ddr_4g = {
 934        .mem_speed = 1600,
 935        .density = 4,
 936        .width = 16,
 937        .banks = 8,
 938        .rowaddr = 15,
 939        .coladdr = 10,
 940        .pagesz = 2,
 941        .trcd = 1310,
 942        .trcmin = 4875,
 943        .trasmin = 3500,
 944};
 945
 946static void ccgr_init(void)
 947{
 948        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 949
 950        writel(0x00C03F3F, &ccm->CCGR0);
 951        writel(0x0030FC03, &ccm->CCGR1);
 952        writel(0x0FFFC000, &ccm->CCGR2);
 953        writel(0x3FF00000, &ccm->CCGR3);
 954        writel(0x00FFF300, &ccm->CCGR4);
 955        writel(0x0F0000C3, &ccm->CCGR5);
 956        writel(0x000003FF, &ccm->CCGR6);
 957}
 958
 959/* Define a minimal structure so that the part number can be read via SPL */
 960struct mfgdata {
 961        unsigned char tsize;
 962        /* size of checksummed part in bytes */
 963        unsigned char ckcnt;
 964        /* checksum corrected byte */
 965        unsigned char cksum;
 966        /* decimal serial number, packed BCD */
 967        unsigned char serial[6];
 968         /* part number, right justified, ASCII */
 969        unsigned char pn[16];
 970};
 971
 972static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
 973{
 974        int remain = len;
 975        unsigned char *sptr = src;
 976        unsigned char *dptr = dst;
 977
 978        while (remain) {
 979                if (*sptr) {
 980                        *dptr = *sptr;
 981                        dptr++;
 982                }
 983                sptr++;
 984                remain--;
 985        }
 986        *dptr = 0x0;
 987}
 988
 989#define CFG_MFG_ADDR_OFFSET     (spi->size - SZ_16K)
 990static bool is_2gb(void)
 991{
 992        struct spi_flash *spi;
 993        int ret;
 994        char buf[sizeof(struct mfgdata)];
 995        struct mfgdata *data = (struct mfgdata *)buf;
 996        unsigned char outbuf[32];
 997
 998        spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
 999                              CONFIG_ENV_SPI_CS,
1000                              CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
1001        ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
1002                             buf);
1003        if (ret)
1004                return false;
1005
1006        /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
1007        conv_ascii(outbuf, data->pn, sizeof(data->pn));
1008        if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
1009                return true;
1010        else
1011                return false;
1012}
1013
1014static void spl_dram_init(int width)
1015{
1016        struct mx6_ddr_sysinfo sysinfo = {
1017                /* width of data bus:0=16,1=32,2=64 */
1018                .dsize = width / 32,
1019                /* config for full 4GB range so that get_mem_size() works */
1020                .cs_density = 32, /* 32Gb per CS */
1021                /* single chip select */
1022                .ncs = 1,
1023                .cs1_mirror = 0,
1024                .rtt_wr = 2,
1025                .rtt_nom = 2,
1026                .walat = 0,
1027                .ralat = 5,
1028                .mif3_mode = 3,
1029                .bi_on = 1,
1030                .sde_to_rst = 0x0d,
1031                .rst_to_cke = 0x20,
1032                .refsel = 1,    /* Refresh cycles at 32KHz */
1033                .refr = 7,      /* 8 refresh commands per refresh cycle */
1034        };
1035
1036        if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
1037                mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1038                mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
1039                return;
1040        }
1041
1042        if (is_mx6dq()) {
1043                mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1044                mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
1045        } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
1046                sysinfo.walat = 1;
1047                mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1048                mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
1049        } else if (is_cpu_type(MXC_CPU_MX6DL)) {
1050                sysinfo.walat = 1;
1051                mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1052                mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
1053        }
1054}
1055
1056void board_init_f(ulong dummy)
1057{
1058        /* setup AIPS and disable watchdog */
1059        arch_cpu_init();
1060
1061        ccgr_init();
1062        gpr_init();
1063
1064        /* iomux and setup of i2c */
1065        board_early_init_f();
1066
1067        /* setup GP timer */
1068        timer_init();
1069
1070        /* UART clocks enabled and gd valid - init serial console */
1071        preloader_console_init();
1072
1073        /* Needed for malloc() to work in SPL prior to board_init_r() */
1074        spl_init();
1075
1076        /* DDR initialization */
1077        if (is_cpu_type(MXC_CPU_MX6SOLO))
1078                spl_dram_init(32);
1079        else
1080                spl_dram_init(64);
1081
1082        /* Clear the BSS. */
1083        memset(__bss_start, 0, __bss_end - __bss_start);
1084
1085        /* load/boot image from boot device */
1086        board_init_r(NULL, 0);
1087}
1088#endif
1089