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9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/mach-imx/spi.h>
14#include <linux/errno.h>
15#include <asm/gpio.h>
16#include <asm/mach-imx/mxc_i2c.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm/mach-imx/boot_mode.h>
19#include <asm/mach-imx/video.h>
20#include <mmc.h>
21#include <fsl_esdhc.h>
22#include <miiphy.h>
23#include <netdev.h>
24#include <asm/arch/mxc_hdmi.h>
25#include <asm/arch/crm_regs.h>
26#include <asm/io.h>
27#include <asm/arch/sys_proto.h>
28#include <i2c.h>
29#include <input.h>
30#include <power/pmic.h>
31#include <power/pfuze100_pmic.h>
32#include "../common/pfuze.h"
33#include <usb.h>
34#include <usb/ehci-ci.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48
49#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51
52#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55
56#define I2C_PMIC 1
57
58#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
59
60#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
61
62#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
63
64int dram_init(void)
65{
66 gd->ram_size = imx_ddr_size();
67 return 0;
68}
69
70static iomux_v3_cfg_t const uart1_pads[] = {
71 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
72 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
73};
74
75static iomux_v3_cfg_t const enet_pads[] = {
76 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91
92 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93};
94
95static void setup_iomux_enet(void)
96{
97 SETUP_IOMUX_PADS(enet_pads);
98
99
100 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
101 mdelay(10);
102 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
103 udelay(100);
104}
105
106static iomux_v3_cfg_t const usdhc2_pads[] = {
107 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
108 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
109 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
110 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
111 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
112 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
113 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
114 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
115 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
116 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
117 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
118};
119
120static iomux_v3_cfg_t const usdhc3_pads[] = {
121 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
122 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
123 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
124 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
125 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
126 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
127 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
128 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
129 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
130 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
131 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
132};
133
134static iomux_v3_cfg_t const usdhc4_pads[] = {
135 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
136 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
137 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
138 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
139 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
140 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
141 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
142 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
143 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
144 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
145};
146
147static iomux_v3_cfg_t const ecspi1_pads[] = {
148 IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
149 IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
150 IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
151 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
152};
153
154static iomux_v3_cfg_t const rgb_pads[] = {
155 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
156 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
157 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
158 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
159 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
160 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
161 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
162 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
163 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
164 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
165 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
166 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
167 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
168 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
169 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
170 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
171 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
172 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
173 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
174 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
175 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
176 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
177 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
178 IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
179 IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
180 IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
181 IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
182 IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
183 IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
184};
185
186static iomux_v3_cfg_t const bl_pads[] = {
187 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
188};
189
190static void enable_backlight(void)
191{
192 SETUP_IOMUX_PADS(bl_pads);
193 gpio_direction_output(DISP0_PWR_EN, 1);
194}
195
196static void enable_rgb(struct display_info_t const *dev)
197{
198 SETUP_IOMUX_PADS(rgb_pads);
199 enable_backlight();
200}
201
202static void enable_lvds(struct display_info_t const *dev)
203{
204 enable_backlight();
205}
206
207static struct i2c_pads_info mx6q_i2c_pad_info1 = {
208 .scl = {
209 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
210 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
211 .gp = IMX_GPIO_NR(4, 12)
212 },
213 .sda = {
214 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
215 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
216 .gp = IMX_GPIO_NR(4, 13)
217 }
218};
219
220static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
221 .scl = {
222 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
223 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
224 .gp = IMX_GPIO_NR(4, 12)
225 },
226 .sda = {
227 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
228 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
229 .gp = IMX_GPIO_NR(4, 13)
230 }
231};
232
233static void setup_spi(void)
234{
235 SETUP_IOMUX_PADS(ecspi1_pads);
236}
237
238iomux_v3_cfg_t const pcie_pads[] = {
239 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
240 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
241};
242
243static void setup_pcie(void)
244{
245 SETUP_IOMUX_PADS(pcie_pads);
246}
247
248iomux_v3_cfg_t const di0_pads[] = {
249 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
250 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
251 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
252};
253
254static void setup_iomux_uart(void)
255{
256 SETUP_IOMUX_PADS(uart1_pads);
257}
258
259#ifdef CONFIG_FSL_ESDHC
260struct fsl_esdhc_cfg usdhc_cfg[3] = {
261 {USDHC2_BASE_ADDR},
262 {USDHC3_BASE_ADDR},
263 {USDHC4_BASE_ADDR},
264};
265
266#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
267#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
268
269int board_mmc_get_env_dev(int devno)
270{
271 return devno - 1;
272}
273
274int board_mmc_getcd(struct mmc *mmc)
275{
276 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
277 int ret = 0;
278
279 switch (cfg->esdhc_base) {
280 case USDHC2_BASE_ADDR:
281 ret = !gpio_get_value(USDHC2_CD_GPIO);
282 break;
283 case USDHC3_BASE_ADDR:
284 ret = !gpio_get_value(USDHC3_CD_GPIO);
285 break;
286 case USDHC4_BASE_ADDR:
287 ret = 1;
288 break;
289 }
290
291 return ret;
292}
293
294int board_mmc_init(bd_t *bis)
295{
296#ifndef CONFIG_SPL_BUILD
297 int ret;
298 int i;
299
300
301
302
303
304
305
306
307 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
308 switch (i) {
309 case 0:
310 SETUP_IOMUX_PADS(usdhc2_pads);
311 gpio_direction_input(USDHC2_CD_GPIO);
312 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
313 break;
314 case 1:
315 SETUP_IOMUX_PADS(usdhc3_pads);
316 gpio_direction_input(USDHC3_CD_GPIO);
317 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
318 break;
319 case 2:
320 SETUP_IOMUX_PADS(usdhc4_pads);
321 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
322 break;
323 default:
324 printf("Warning: you configured more USDHC controllers"
325 "(%d) then supported by the board (%d)\n",
326 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
327 return -EINVAL;
328 }
329
330 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
331 if (ret)
332 return ret;
333 }
334
335 return 0;
336#else
337 struct src *psrc = (struct src *)SRC_BASE_ADDR;
338 unsigned reg = readl(&psrc->sbmr1) >> 11;
339
340
341
342
343
344
345
346
347
348 switch (reg & 0x3) {
349 case 0x1:
350 SETUP_IOMUX_PADS(usdhc2_pads);
351 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
352 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
353 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
354 break;
355 case 0x2:
356 SETUP_IOMUX_PADS(usdhc3_pads);
357 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
358 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
359 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
360 break;
361 case 0x3:
362 SETUP_IOMUX_PADS(usdhc4_pads);
363 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
364 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
365 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
366 break;
367 }
368
369 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
370#endif
371}
372#endif
373
374static int ar8031_phy_fixup(struct phy_device *phydev)
375{
376 unsigned short val;
377
378
379 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
380 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
381 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
382
383 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
384 val &= 0xffe3;
385 val |= 0x18;
386 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
387
388
389 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
390 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
391 val |= 0x0100;
392 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
393
394 return 0;
395}
396
397int board_phy_config(struct phy_device *phydev)
398{
399 ar8031_phy_fixup(phydev);
400
401 if (phydev->drv->config)
402 phydev->drv->config(phydev);
403
404 return 0;
405}
406
407#if defined(CONFIG_VIDEO_IPUV3)
408static void disable_lvds(struct display_info_t const *dev)
409{
410 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
411
412 int reg = readl(&iomux->gpr[2]);
413
414 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
415 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
416
417 writel(reg, &iomux->gpr[2]);
418}
419
420static void do_enable_hdmi(struct display_info_t const *dev)
421{
422 disable_lvds(dev);
423 imx_enable_hdmi_phy();
424}
425
426struct display_info_t const displays[] = {{
427 .bus = -1,
428 .addr = 0,
429 .pixfmt = IPU_PIX_FMT_RGB666,
430 .detect = NULL,
431 .enable = enable_lvds,
432 .mode = {
433 .name = "Hannstar-XGA",
434 .refresh = 60,
435 .xres = 1024,
436 .yres = 768,
437 .pixclock = 15384,
438 .left_margin = 160,
439 .right_margin = 24,
440 .upper_margin = 29,
441 .lower_margin = 3,
442 .hsync_len = 136,
443 .vsync_len = 6,
444 .sync = FB_SYNC_EXT,
445 .vmode = FB_VMODE_NONINTERLACED
446} }, {
447 .bus = -1,
448 .addr = 0,
449 .pixfmt = IPU_PIX_FMT_RGB24,
450 .detect = detect_hdmi,
451 .enable = do_enable_hdmi,
452 .mode = {
453 .name = "HDMI",
454 .refresh = 60,
455 .xres = 1024,
456 .yres = 768,
457 .pixclock = 15384,
458 .left_margin = 160,
459 .right_margin = 24,
460 .upper_margin = 29,
461 .lower_margin = 3,
462 .hsync_len = 136,
463 .vsync_len = 6,
464 .sync = FB_SYNC_EXT,
465 .vmode = FB_VMODE_NONINTERLACED
466} }, {
467 .bus = 0,
468 .addr = 0,
469 .pixfmt = IPU_PIX_FMT_RGB24,
470 .detect = NULL,
471 .enable = enable_rgb,
472 .mode = {
473 .name = "SEIKO-WVGA",
474 .refresh = 60,
475 .xres = 800,
476 .yres = 480,
477 .pixclock = 29850,
478 .left_margin = 89,
479 .right_margin = 164,
480 .upper_margin = 23,
481 .lower_margin = 10,
482 .hsync_len = 10,
483 .vsync_len = 10,
484 .sync = 0,
485 .vmode = FB_VMODE_NONINTERLACED
486} } };
487size_t display_count = ARRAY_SIZE(displays);
488
489static void setup_display(void)
490{
491 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
492 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
493 int reg;
494
495
496 SETUP_IOMUX_PADS(di0_pads);
497
498 enable_ipu_clock();
499 imx_setup_hdmi();
500
501
502 reg = readl(&mxc_ccm->CCGR3);
503 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
504 writel(reg, &mxc_ccm->CCGR3);
505
506
507 reg = readl(&mxc_ccm->cs2cdr);
508 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
509 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
510 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
511 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
512 writel(reg, &mxc_ccm->cs2cdr);
513
514 reg = readl(&mxc_ccm->cscmr2);
515 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
516 writel(reg, &mxc_ccm->cscmr2);
517
518 reg = readl(&mxc_ccm->chsccdr);
519 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
520 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
521 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
522 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
523 writel(reg, &mxc_ccm->chsccdr);
524
525 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
526 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
527 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
528 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
529 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
530 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
531 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
532 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
533 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
534 writel(reg, &iomux->gpr[2]);
535
536 reg = readl(&iomux->gpr[3]);
537 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
538 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
539 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
540 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
541 writel(reg, &iomux->gpr[3]);
542}
543#endif
544
545
546
547
548
549int overwrite_console(void)
550{
551 return 1;
552}
553
554int board_eth_init(bd_t *bis)
555{
556 setup_iomux_enet();
557 setup_pcie();
558
559 return cpu_eth_init(bis);
560}
561
562#ifdef CONFIG_USB_EHCI_MX6
563#define USB_OTHERREGS_OFFSET 0x800
564#define UCTRL_PWR_POL (1 << 9)
565
566static iomux_v3_cfg_t const usb_otg_pads[] = {
567 IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
568 IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
569};
570
571static iomux_v3_cfg_t const usb_hc1_pads[] = {
572 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
573};
574
575static void setup_usb(void)
576{
577 SETUP_IOMUX_PADS(usb_otg_pads);
578
579
580
581
582
583 imx_iomux_set_gpr_register(1, 13, 1, 0);
584
585 SETUP_IOMUX_PADS(usb_hc1_pads);
586}
587
588int board_ehci_hcd_init(int port)
589{
590 u32 *usbnc_usb_ctrl;
591
592 if (port > 1)
593 return -EINVAL;
594
595 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
596 port * 4);
597
598 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
599
600 return 0;
601}
602
603int board_ehci_power(int port, int on)
604{
605 switch (port) {
606 case 0:
607 break;
608 case 1:
609 if (on)
610 gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
611 else
612 gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
613 break;
614 default:
615 printf("MXC USB port %d not yet supported\n", port);
616 return -EINVAL;
617 }
618
619 return 0;
620}
621#endif
622
623int board_early_init_f(void)
624{
625 setup_iomux_uart();
626
627 return 0;
628}
629
630int board_init(void)
631{
632
633 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
634
635#ifdef CONFIG_MXC_SPI
636 setup_spi();
637#endif
638 if (is_mx6dq() || is_mx6dqp())
639 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
640 else
641 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
642#if defined(CONFIG_VIDEO_IPUV3)
643 setup_display();
644#endif
645#ifdef CONFIG_USB_EHCI_MX6
646 setup_usb();
647#endif
648
649 return 0;
650}
651
652int power_init_board(void)
653{
654 struct pmic *p;
655 unsigned int reg;
656 int ret;
657
658 p = pfuze_common_init(I2C_PMIC);
659 if (!p)
660 return -ENODEV;
661
662 ret = pfuze_mode_init(p, APS_PFM);
663 if (ret < 0)
664 return ret;
665
666
667 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
668 reg &= ~LDO_VOL_MASK;
669 reg |= LDOB_2_80V;
670 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
671
672
673 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
674 reg &= ~LDO_VOL_MASK;
675 reg |= LDOB_3_00V;
676 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
677
678 return 0;
679}
680
681#ifdef CONFIG_MXC_SPI
682int board_spi_cs_gpio(unsigned bus, unsigned cs)
683{
684 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
685}
686#endif
687
688#ifdef CONFIG_CMD_BMODE
689static const struct boot_mode board_boot_modes[] = {
690
691 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
692 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
693
694 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
695 {NULL, 0},
696};
697#endif
698
699int board_late_init(void)
700{
701#ifdef CONFIG_CMD_BMODE
702 add_board_boot_modes(board_boot_modes);
703#endif
704
705#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
706 env_set("board_name", "SABRESD");
707
708 if (is_mx6dqp())
709 env_set("board_rev", "MX6QP");
710 else if (is_mx6dq())
711 env_set("board_rev", "MX6Q");
712 else if (is_mx6sdl())
713 env_set("board_rev", "MX6DL");
714#endif
715
716 return 0;
717}
718
719int checkboard(void)
720{
721 puts("Board: MX6-SabreSD\n");
722 return 0;
723}
724
725#ifdef CONFIG_SPL_BUILD
726#include <asm/arch/mx6-ddr.h>
727#include <spl.h>
728#include <libfdt.h>
729
730#ifdef CONFIG_SPL_OS_BOOT
731int spl_start_uboot(void)
732{
733 gpio_direction_input(KEY_VOL_UP);
734
735
736 return gpio_get_value(KEY_VOL_UP);
737}
738#endif
739
740static void ccgr_init(void)
741{
742 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
743
744 writel(0x00C03F3F, &ccm->CCGR0);
745 writel(0x0030FC03, &ccm->CCGR1);
746 writel(0x0FFFC000, &ccm->CCGR2);
747 writel(0x3FF00000, &ccm->CCGR3);
748 writel(0x00FFF300, &ccm->CCGR4);
749 writel(0x0F0000C3, &ccm->CCGR5);
750 writel(0x000003FF, &ccm->CCGR6);
751}
752
753static int mx6q_dcd_table[] = {
754 0x020e0798, 0x000C0000,
755 0x020e0758, 0x00000000,
756 0x020e0588, 0x00000030,
757 0x020e0594, 0x00000030,
758 0x020e056c, 0x00000030,
759 0x020e0578, 0x00000030,
760 0x020e074c, 0x00000030,
761 0x020e057c, 0x00000030,
762 0x020e058c, 0x00000000,
763 0x020e059c, 0x00000030,
764 0x020e05a0, 0x00000030,
765 0x020e078c, 0x00000030,
766 0x020e0750, 0x00020000,
767 0x020e05a8, 0x00000030,
768 0x020e05b0, 0x00000030,
769 0x020e0524, 0x00000030,
770 0x020e051c, 0x00000030,
771 0x020e0518, 0x00000030,
772 0x020e050c, 0x00000030,
773 0x020e05b8, 0x00000030,
774 0x020e05c0, 0x00000030,
775 0x020e0774, 0x00020000,
776 0x020e0784, 0x00000030,
777 0x020e0788, 0x00000030,
778 0x020e0794, 0x00000030,
779 0x020e079c, 0x00000030,
780 0x020e07a0, 0x00000030,
781 0x020e07a4, 0x00000030,
782 0x020e07a8, 0x00000030,
783 0x020e0748, 0x00000030,
784 0x020e05ac, 0x00000030,
785 0x020e05b4, 0x00000030,
786 0x020e0528, 0x00000030,
787 0x020e0520, 0x00000030,
788 0x020e0514, 0x00000030,
789 0x020e0510, 0x00000030,
790 0x020e05bc, 0x00000030,
791 0x020e05c4, 0x00000030,
792 0x021b0800, 0xa1390003,
793 0x021b080c, 0x001F001F,
794 0x021b0810, 0x001F001F,
795 0x021b480c, 0x001F001F,
796 0x021b4810, 0x001F001F,
797 0x021b083c, 0x43270338,
798 0x021b0840, 0x03200314,
799 0x021b483c, 0x431A032F,
800 0x021b4840, 0x03200263,
801 0x021b0848, 0x4B434748,
802 0x021b4848, 0x4445404C,
803 0x021b0850, 0x38444542,
804 0x021b4850, 0x4935493A,
805 0x021b081c, 0x33333333,
806 0x021b0820, 0x33333333,
807 0x021b0824, 0x33333333,
808 0x021b0828, 0x33333333,
809 0x021b481c, 0x33333333,
810 0x021b4820, 0x33333333,
811 0x021b4824, 0x33333333,
812 0x021b4828, 0x33333333,
813 0x021b08b8, 0x00000800,
814 0x021b48b8, 0x00000800,
815 0x021b0004, 0x00020036,
816 0x021b0008, 0x09444040,
817 0x021b000c, 0x555A7975,
818 0x021b0010, 0xFF538F64,
819 0x021b0014, 0x01FF00DB,
820 0x021b0018, 0x00001740,
821 0x021b001c, 0x00008000,
822 0x021b002c, 0x000026d2,
823 0x021b0030, 0x005A1023,
824 0x021b0040, 0x00000027,
825 0x021b0000, 0x831A0000,
826 0x021b001c, 0x04088032,
827 0x021b001c, 0x00008033,
828 0x021b001c, 0x00048031,
829 0x021b001c, 0x09408030,
830 0x021b001c, 0x04008040,
831 0x021b0020, 0x00005800,
832 0x021b0818, 0x00011117,
833 0x021b4818, 0x00011117,
834 0x021b0004, 0x00025576,
835 0x021b0404, 0x00011006,
836 0x021b001c, 0x00000000,
837};
838
839static int mx6qp_dcd_table[] = {
840 0x020e0798, 0x000c0000,
841 0x020e0758, 0x00000000,
842 0x020e0588, 0x00000030,
843 0x020e0594, 0x00000030,
844 0x020e056c, 0x00000030,
845 0x020e0578, 0x00000030,
846 0x020e074c, 0x00000030,
847 0x020e057c, 0x00000030,
848 0x020e058c, 0x00000000,
849 0x020e059c, 0x00000030,
850 0x020e05a0, 0x00000030,
851 0x020e078c, 0x00000030,
852 0x020e0750, 0x00020000,
853 0x020e05a8, 0x00000030,
854 0x020e05b0, 0x00000030,
855 0x020e0524, 0x00000030,
856 0x020e051c, 0x00000030,
857 0x020e0518, 0x00000030,
858 0x020e050c, 0x00000030,
859 0x020e05b8, 0x00000030,
860 0x020e05c0, 0x00000030,
861 0x020e0774, 0x00020000,
862 0x020e0784, 0x00000030,
863 0x020e0788, 0x00000030,
864 0x020e0794, 0x00000030,
865 0x020e079c, 0x00000030,
866 0x020e07a0, 0x00000030,
867 0x020e07a4, 0x00000030,
868 0x020e07a8, 0x00000030,
869 0x020e0748, 0x00000030,
870 0x020e05ac, 0x00000030,
871 0x020e05b4, 0x00000030,
872 0x020e0528, 0x00000030,
873 0x020e0520, 0x00000030,
874 0x020e0514, 0x00000030,
875 0x020e0510, 0x00000030,
876 0x020e05bc, 0x00000030,
877 0x020e05c4, 0x00000030,
878 0x021b0800, 0xa1390003,
879 0x021b080c, 0x001b001e,
880 0x021b0810, 0x002e0029,
881 0x021b480c, 0x001b002a,
882 0x021b4810, 0x0019002c,
883 0x021b083c, 0x43240334,
884 0x021b0840, 0x0324031a,
885 0x021b483c, 0x43340344,
886 0x021b4840, 0x03280276,
887 0x021b0848, 0x44383A3E,
888 0x021b4848, 0x3C3C3846,
889 0x021b0850, 0x2e303230,
890 0x021b4850, 0x38283E34,
891 0x021b081c, 0x33333333,
892 0x021b0820, 0x33333333,
893 0x021b0824, 0x33333333,
894 0x021b0828, 0x33333333,
895 0x021b481c, 0x33333333,
896 0x021b4820, 0x33333333,
897 0x021b4824, 0x33333333,
898 0x021b4828, 0x33333333,
899 0x021b08c0, 0x24912249,
900 0x021b48c0, 0x24914289,
901 0x021b08b8, 0x00000800,
902 0x021b48b8, 0x00000800,
903 0x021b0004, 0x00020036,
904 0x021b0008, 0x24444040,
905 0x021b000c, 0x555A7955,
906 0x021b0010, 0xFF320F64,
907 0x021b0014, 0x01ff00db,
908 0x021b0018, 0x00001740,
909 0x021b001c, 0x00008000,
910 0x021b002c, 0x000026d2,
911 0x021b0030, 0x005A1023,
912 0x021b0040, 0x00000027,
913 0x021b0400, 0x14420000,
914 0x021b0000, 0x831A0000,
915 0x021b0890, 0x00400C58,
916 0x00bb0008, 0x00000000,
917 0x00bb000c, 0x2891E41A,
918 0x00bb0038, 0x00000564,
919 0x00bb0014, 0x00000040,
920 0x00bb0028, 0x00000020,
921 0x00bb002c, 0x00000020,
922 0x021b001c, 0x04088032,
923 0x021b001c, 0x00008033,
924 0x021b001c, 0x00048031,
925 0x021b001c, 0x09408030,
926 0x021b001c, 0x04008040,
927 0x021b0020, 0x00005800,
928 0x021b0818, 0x00011117,
929 0x021b4818, 0x00011117,
930 0x021b0004, 0x00025576,
931 0x021b0404, 0x00011006,
932 0x021b001c, 0x00000000,
933};
934
935static int mx6dl_dcd_table[] = {
936 0x020e0774, 0x000C0000,
937 0x020e0754, 0x00000000,
938 0x020e04ac, 0x00000030,
939 0x020e04b0, 0x00000030,
940 0x020e0464, 0x00000030,
941 0x020e0490, 0x00000030,
942 0x020e074c, 0x00000030,
943 0x020e0494, 0x00000030,
944 0x020e04a0, 0x00000000,
945 0x020e04b4, 0x00000030,
946 0x020e04b8, 0x00000030,
947 0x020e076c, 0x00000030,
948 0x020e0750, 0x00020000,
949 0x020e04bc, 0x00000030,
950 0x020e04c0, 0x00000030,
951 0x020e04c4, 0x00000030,
952 0x020e04c8, 0x00000030,
953 0x020e04cc, 0x00000030,
954 0x020e04d0, 0x00000030,
955 0x020e04d4, 0x00000030,
956 0x020e04d8, 0x00000030,
957 0x020e0760, 0x00020000,
958 0x020e0764, 0x00000030,
959 0x020e0770, 0x00000030,
960 0x020e0778, 0x00000030,
961 0x020e077c, 0x00000030,
962 0x020e0780, 0x00000030,
963 0x020e0784, 0x00000030,
964 0x020e078c, 0x00000030,
965 0x020e0748, 0x00000030,
966 0x020e0470, 0x00000030,
967 0x020e0474, 0x00000030,
968 0x020e0478, 0x00000030,
969 0x020e047c, 0x00000030,
970 0x020e0480, 0x00000030,
971 0x020e0484, 0x00000030,
972 0x020e0488, 0x00000030,
973 0x020e048c, 0x00000030,
974 0x021b0800, 0xa1390003,
975 0x021b080c, 0x001F001F,
976 0x021b0810, 0x001F001F,
977 0x021b480c, 0x001F001F,
978 0x021b4810, 0x001F001F,
979 0x021b083c, 0x4220021F,
980 0x021b0840, 0x0207017E,
981 0x021b483c, 0x4201020C,
982 0x021b4840, 0x01660172,
983 0x021b0848, 0x4A4D4E4D,
984 0x021b4848, 0x4A4F5049,
985 0x021b0850, 0x3F3C3D31,
986 0x021b4850, 0x3238372B,
987 0x021b081c, 0x33333333,
988 0x021b0820, 0x33333333,
989 0x021b0824, 0x33333333,
990 0x021b0828, 0x33333333,
991 0x021b481c, 0x33333333,
992 0x021b4820, 0x33333333,
993 0x021b4824, 0x33333333,
994 0x021b4828, 0x33333333,
995 0x021b08b8, 0x00000800,
996 0x021b48b8, 0x00000800,
997 0x021b0004, 0x0002002D,
998 0x021b0008, 0x00333030,
999 0x021b000c, 0x3F435313,
1000 0x021b0010, 0xB66E8B63,
1001 0x021b0014, 0x01FF00DB,
1002 0x021b0018, 0x00001740,
1003 0x021b001c, 0x00008000,
1004 0x021b002c, 0x000026d2,
1005 0x021b0030, 0x00431023,
1006 0x021b0040, 0x00000027,
1007 0x021b0000, 0x831A0000,
1008 0x021b001c, 0x04008032,
1009 0x021b001c, 0x00008033,
1010 0x021b001c, 0x00048031,
1011 0x021b001c, 0x05208030,
1012 0x021b001c, 0x04008040,
1013 0x021b0020, 0x00005800,
1014 0x021b0818, 0x00011117,
1015 0x021b4818, 0x00011117,
1016 0x021b0004, 0x0002556D,
1017 0x021b0404, 0x00011006,
1018 0x021b001c, 0x00000000,
1019};
1020
1021static void ddr_init(int *table, int size)
1022{
1023 int i;
1024
1025 for (i = 0; i < size / 2 ; i++)
1026 writel(table[2 * i + 1], table[2 * i]);
1027}
1028
1029static void spl_dram_init(void)
1030{
1031 if (is_mx6dq())
1032 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1033 else if (is_mx6dqp())
1034 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1035 else if (is_mx6sdl())
1036 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1037}
1038
1039void board_init_f(ulong dummy)
1040{
1041
1042 spl_dram_init();
1043
1044
1045 arch_cpu_init();
1046
1047 ccgr_init();
1048 gpr_init();
1049
1050
1051 board_early_init_f();
1052
1053
1054 timer_init();
1055
1056
1057 preloader_console_init();
1058
1059
1060 memset(__bss_start, 0, __bss_end - __bss_start);
1061
1062
1063 board_init_r(NULL, 0);
1064}
1065#endif
1066
