LXR uboot/board/freescale/t104xrdb/diu.c

   1/*
   2 * Copyright 2014 Freescale Semiconductor, Inc.
   3 * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <asm/io.h>
   9#include <common.h>
  10#include <command.h>
  11#include <fsl_diu_fb.h>
  12#include <linux/ctype.h>
  13#include <video_fb.h>
  14
  15#include "../common/diu_ch7301.h"
  16
  17#include "cpld.h"
  18#include "t104xrdb.h"
  19
  20/*
  21 * DIU Area Descriptor
  22 *
  23 * Note that we need to byte-swap the value before it's written to the AD
  24 * register. So even though the registers don't look like they're in the same
  25 * bit positions as they are on the MPC8610, the same value is written to the
  26 * AD register on the MPC8610 and on the P1022.
  27 */
  28#define AD_BYTE_F               0x10000000
  29#define AD_ALPHA_C_SHIFT        25
  30#define AD_BLUE_C_SHIFT         23
  31#define AD_GREEN_C_SHIFT        21
  32#define AD_RED_C_SHIFT          19
  33#define AD_PIXEL_S_SHIFT        16
  34#define AD_COMP_3_SHIFT         12
  35#define AD_COMP_2_SHIFT         8
  36#define AD_COMP_1_SHIFT         4
  37#define AD_COMP_0_SHIFT         0
  38
  39void diu_set_pixel_clock(unsigned int pixclock)
  40{
  41        unsigned long speed_ccb, temp;
  42        u32 pixval;
  43        int ret;
  44
  45        speed_ccb = get_bus_freq(0);
  46        temp = 1000000000 / pixclock;
  47        temp *= 1000;
  48        pixval = speed_ccb / temp;
  49
  50        /* Program HDMI encoder */
  51        ret = diu_set_dvi_encoder(temp);
  52        if (ret) {
  53                puts("Failed to set DVI encoder\n");
  54                return;
  55        }
  56
  57        /* Program pixel clock */
  58        out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
  59                 ((pixval << PXCK_BITS_START) & PXCK_MASK));
  60
  61        /* enable clock*/
  62        out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
  63                 ((pixval << PXCK_BITS_START) & PXCK_MASK));
  64}
  65
  66int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  67{
  68        u32 pixel_format;
  69        u8 sw;
  70
  71        /*Configure Display ouput port as HDMI*/
  72        sw = CPLD_READ(sfp_ctl_status);
  73        CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
  74
  75        pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  76                (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  77                (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  78                (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  79                (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  80
  81        printf("DIU: Switching to monitor DVI @ %ux%u\n",  xres, yres);
  82
  83        return fsl_diu_init(xres, yres, pixel_format, 0);
  84}
  85