LXR uboot/board/freescale/t208xqds/tlb.c

   1/*
   2 * Copyright 2008-2013 Freescale Semiconductor, Inc.
   3 *
   4 * (C) Copyright 2000
   5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <asm/mmu.h>
  12
  13struct fsl_e_tlb_entry tlb_table[] = {
  14        /* TLB 0 - for temp stack in cache */
  15        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  16                      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  17                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18                      0, 0, BOOKE_PAGESZ_4K, 0),
  19        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20                      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  21                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                      0, 0, BOOKE_PAGESZ_4K, 0),
  23        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24                      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  25                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26                      0, 0, BOOKE_PAGESZ_4K, 0),
  27        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28                      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  29                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
  30                      0, 0, BOOKE_PAGESZ_4K, 0),
  31
  32        /* TLB 1 */
  33        /* *I*** - Covers boot page */
  34#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  35        /*
  36         * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  37         * SRAM is at 0xfff00000, it covered the 0xfffff000.
  38         */
  39        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  40                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41                      0, 0, BOOKE_PAGESZ_1M, 1),
  42#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  43        /*
  44         * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  45         * space is at 0xfff00000, it covered the 0xfffff000.
  46         */
  47        SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  48                      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  49                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  50                      0, 0, BOOKE_PAGESZ_1M, 1),
  51#else
  52        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  53                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                      0, 0, BOOKE_PAGESZ_4K, 1),
  55#endif
  56
  57        /* *I*G* - CCSRBAR */
  58        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  59                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60                      0, 1, BOOKE_PAGESZ_16M, 1),
  61
  62        /* *I*G* - Flash, localbus */
  63        /* This will be changed to *I*G* after relocation to RAM. */
  64        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  65                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  66                      0, 2, BOOKE_PAGESZ_256M, 1),
  67
  68#ifndef CONFIG_SPL_BUILD
  69        /* *I*G* - PCIe 1, 0x80000000 */
  70        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  71                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72                      0, 3, BOOKE_PAGESZ_512M, 1),
  73
  74        /* *I*G* - PCIe 2, 0xa0000000 */
  75        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
  76                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77                      0, 4, BOOKE_PAGESZ_256M, 1),
  78
  79        /* *I*G* - PCIe 3, 0xb0000000 */
  80        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  81                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82                      0, 5, BOOKE_PAGESZ_256M, 1),
  83
  84
  85        /* *I*G* - PCIe 4, 0xc0000000 */
  86        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
  87                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88                      0, 6, BOOKE_PAGESZ_256M, 1),
  89
  90        /* *I*G* - PCI I/O */
  91        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  92                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  93                      0, 7, BOOKE_PAGESZ_256K, 1),
  94
  95        /* Bman/Qman */
  96#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  97        SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  98                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
  99                      0, 9, BOOKE_PAGESZ_16M, 1),
 100        SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
 101                      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
 102                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 103                      0, 10, BOOKE_PAGESZ_16M, 1),
 104#endif
 105#ifdef CONFIG_SYS_QMAN_MEM_PHYS
 106        SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 107                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 108                      0, 11, BOOKE_PAGESZ_16M, 1),
 109        SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
 110                      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
 111                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 112                      0, 12, BOOKE_PAGESZ_16M, 1),
 113#endif
 114#endif
 115#ifdef CONFIG_SYS_DCSRBAR_PHYS
 116        SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 117                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 118                      0, 13, BOOKE_PAGESZ_32M, 1),
 119#endif
 120#ifdef CONFIG_SYS_NAND_BASE
 121        /*
 122         * *I*G - NAND
 123         * entry 14 and 15 has been used hard coded, they will be disabled
 124         * in cpu_init_f, so we use entry 16 for nand.
 125         */
 126        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 127                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 128                      0, 16, BOOKE_PAGESZ_64K, 1),
 129#endif
 130#ifdef QIXIS_BASE_PHYS
 131        SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 132                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 133                      0, 17, BOOKE_PAGESZ_4K, 1),
 134#endif
 135#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 136        /*
 137         * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 138         * fetching ucode and ENV from master
 139         */
 140        SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
 141                      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 142                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 143                      0, 18, BOOKE_PAGESZ_1M, 1),
 144#endif
 145
 146#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 147        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 148                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 149                      0, 19, BOOKE_PAGESZ_2G, 1)
 150#endif
 151};
 152
 153int num_tlb_entries = ARRAY_SIZE(tlb_table);
 154