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7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/iomux-vf610.h>
11#include <asm/arch/ddrmc-vf610.h>
12#include <asm/arch/crm_regs.h>
13#include <asm/arch/clock.h>
14#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <miiphy.h>
17#include <netdev.h>
18#include <i2c.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
23 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
24
25#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
26 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
27
28#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
29 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
30
31static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
32
33 { DDRMC_CR97_WRLVL_EN, 97 },
34 { DDRMC_CR98_WRLVL_DL_0(0), 98 },
35 { DDRMC_CR99_WRLVL_DL_1(0), 99 },
36 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
37 { DDRMC_CR105_RDLVL_DL_0(0), 105 },
38 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
39 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
40
41 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
42 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
43 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
44 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
45 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
46 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
47 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
48 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
49 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
50 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
51 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
52 { DDRMC_CR126_PHY_RDLAT(8), 126 },
53 { DDRMC_CR132_WRLAT_ADJ(5) |
54 DDRMC_CR132_RDLAT_ADJ(6), 132 },
55 { DDRMC_CR137_PHYCTL_DL(2), 137 },
56 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
57 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
58 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
59 DDRMC_CR139_PHY_WRLV_DLL(3) |
60 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
61 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
62 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
63 DDRMC_CR143_RDLV_MXDL(128), 143 },
64 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
65 DDRMC_CR144_PHY_RDLV_DLL(3) |
66 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
67 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
68 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
69 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
70 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
71 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
72 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
73
74 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
75 DDRMC_CR154_PAD_ZQ_MODE(1) |
76 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
77 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
78 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
79 { DDRMC_CR158_TWR(6), 158 },
80 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
81 DDRMC_CR161_TODTH_WR(2), 161 },
82
83 { 0, -1 }
84};
85
86int dram_init(void)
87{
88 static const struct ddr3_jedec_timings timings = {
89 .tinit = 5,
90 .trst_pwron = 80000,
91 .cke_inactive = 200000,
92 .wrlat = 5,
93 .caslat_lin = 12,
94 .trc = 21,
95 .trrd = 4,
96 .tccd = 4,
97 .tbst_int_interval = 0,
98 .tfaw = 20,
99 .trp = 6,
100 .twtr = 4,
101 .tras_min = 15,
102 .tmrd = 4,
103 .trtp = 4,
104 .tras_max = 28080,
105 .tmod = 12,
106 .tckesr = 4,
107 .tcke = 3,
108 .trcd_int = 6,
109 .tras_lockout = 0,
110 .tdal = 12,
111 .bstlen = 3,
112 .tdll = 512,
113 .trp_ab = 6,
114 .tref = 3120,
115 .trfc = 44,
116 .tref_int = 0,
117 .tpdex = 3,
118 .txpdll = 10,
119 .txsnr = 48,
120 .txsr = 468,
121 .cksrx = 5,
122 .cksre = 5,
123 .freq_chg_en = 0,
124 .zqcl = 256,
125 .zqinit = 512,
126 .zqcs = 64,
127 .ref_per_zq = 64,
128 .zqcs_rotate = 0,
129 .aprebit = 10,
130 .cmd_age_cnt = 64,
131 .age_cnt = 64,
132 .q_fullness = 7,
133 .odt_rd_mapcs0 = 0,
134 .odt_wr_mapcs0 = 1,
135 .wlmrd = 40,
136 .wldqsen = 25,
137 };
138
139 ddrmc_setup_iomux(NULL, 0);
140
141 ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
142 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
143
144 return 0;
145}
146
147static void setup_iomux_uart(void)
148{
149 static const iomux_v3_cfg_t uart1_pads[] = {
150 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
151 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
152 };
153
154 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
155}
156
157static void setup_iomux_enet(void)
158{
159 static const iomux_v3_cfg_t enet0_pads[] = {
160 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
161 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
162 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
163 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
164 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
165 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
166 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
167 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
168 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
169 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
170 };
171
172 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
173}
174
175static void setup_iomux_i2c(void)
176{
177 static const iomux_v3_cfg_t i2c0_pads[] = {
178 VF610_PAD_PTB14__I2C0_SCL,
179 VF610_PAD_PTB15__I2C0_SDA,
180 };
181
182 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
183}
184
185#ifdef CONFIG_NAND_VF610_NFC
186static void setup_iomux_nfc(void)
187{
188 static const iomux_v3_cfg_t nfc_pads[] = {
189 VF610_PAD_PTD31__NF_IO15,
190 VF610_PAD_PTD30__NF_IO14,
191 VF610_PAD_PTD29__NF_IO13,
192 VF610_PAD_PTD28__NF_IO12,
193 VF610_PAD_PTD27__NF_IO11,
194 VF610_PAD_PTD26__NF_IO10,
195 VF610_PAD_PTD25__NF_IO9,
196 VF610_PAD_PTD24__NF_IO8,
197 VF610_PAD_PTD23__NF_IO7,
198 VF610_PAD_PTD22__NF_IO6,
199 VF610_PAD_PTD21__NF_IO5,
200 VF610_PAD_PTD20__NF_IO4,
201 VF610_PAD_PTD19__NF_IO3,
202 VF610_PAD_PTD18__NF_IO2,
203 VF610_PAD_PTD17__NF_IO1,
204 VF610_PAD_PTD16__NF_IO0,
205 VF610_PAD_PTB24__NF_WE_B,
206 VF610_PAD_PTB25__NF_CE0_B,
207 VF610_PAD_PTB27__NF_RE_B,
208 VF610_PAD_PTC26__NF_RB_B,
209 VF610_PAD_PTC27__NF_ALE,
210 VF610_PAD_PTC28__NF_CLE
211 };
212
213 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
214}
215#endif
216
217
218static void setup_iomux_qspi(void)
219{
220 static const iomux_v3_cfg_t qspi0_pads[] = {
221 VF610_PAD_PTD0__QSPI0_A_QSCK,
222 VF610_PAD_PTD1__QSPI0_A_CS0,
223 VF610_PAD_PTD2__QSPI0_A_DATA3,
224 VF610_PAD_PTD3__QSPI0_A_DATA2,
225 VF610_PAD_PTD4__QSPI0_A_DATA1,
226 VF610_PAD_PTD5__QSPI0_A_DATA0,
227 VF610_PAD_PTD7__QSPI0_B_QSCK,
228 VF610_PAD_PTD8__QSPI0_B_CS0,
229 VF610_PAD_PTD9__QSPI0_B_DATA3,
230 VF610_PAD_PTD10__QSPI0_B_DATA2,
231 VF610_PAD_PTD11__QSPI0_B_DATA1,
232 VF610_PAD_PTD12__QSPI0_B_DATA0,
233 };
234
235 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
236}
237
238#ifdef CONFIG_FSL_ESDHC
239struct fsl_esdhc_cfg esdhc_cfg[1] = {
240 {ESDHC1_BASE_ADDR},
241};
242
243int board_mmc_getcd(struct mmc *mmc)
244{
245
246 return 1;
247}
248
249int board_mmc_init(bd_t *bis)
250{
251 static const iomux_v3_cfg_t esdhc1_pads[] = {
252 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
253 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
254 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
255 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
256 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
257 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
258 };
259
260 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
261
262 imx_iomux_v3_setup_multiple_pads(
263 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
264
265 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
266}
267#endif
268
269static void clock_init(void)
270{
271 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
272 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
273
274 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
275 CCM_CCGR0_UART1_CTRL_MASK);
276 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
277 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
278 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
279 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
280 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
281 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
282 CCM_CCGR2_QSPI0_CTRL_MASK);
283 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
284 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
285 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
286 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
287 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
288 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
289 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
290 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
291 CCM_CCGR7_SDHC1_CTRL_MASK);
292 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
293 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
294 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
295 CCM_CCGR10_NFC_CTRL_MASK);
296
297 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
298 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
299 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
300 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
301
302 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
303 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
304 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
305 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
306 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
307 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
308 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
309 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
310 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
311 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
312 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
313 CCM_CACRR_ARM_CLK_DIV(0));
314 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
315 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
316 CCM_CSCMR1_NFC_CLK_SEL(0));
317 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
318 CCM_CSCDR1_RMII_CLK_EN);
319 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
320 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
321 CCM_CSCDR2_NFC_EN);
322 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
323 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
324 CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
325 CCM_CSCDR3_NFC_PRE_DIV(5));
326 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
327 CCM_CSCMR2_RMII_CLK_SEL(0));
328}
329
330static void mscm_init(void)
331{
332 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
333 int i;
334
335 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
336 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
337}
338
339int board_phy_config(struct phy_device *phydev)
340{
341 if (phydev->drv->config)
342 phydev->drv->config(phydev);
343
344 return 0;
345}
346
347int board_early_init_f(void)
348{
349 clock_init();
350 mscm_init();
351
352 setup_iomux_uart();
353 setup_iomux_enet();
354 setup_iomux_i2c();
355 setup_iomux_qspi();
356#ifdef CONFIG_NAND_VF610_NFC
357 setup_iomux_nfc();
358#endif
359
360 return 0;
361}
362
363int board_init(void)
364{
365 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
366
367
368 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
369
370
371
372
373
374
375
376
377 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
378
379 return 0;
380}
381
382int checkboard(void)
383{
384 puts("Board: vf610twr\n");
385
386 return 0;
387}
388
