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13#include <common.h>
14
15#include <asm/io.h>
16#include <pci.h>
17#include <video_fb.h>
18#include "videomodes.h"
19#include <mb862xx.h>
20
21#if defined(CONFIG_POST)
22#include <post.h>
23#endif
24
25
26
27
28GraphicDevice mb862xx;
29
30
31
32
33#define VIDEO_MEM_SIZE 0x01FC0000
34
35#if defined(CONFIG_PCI)
36#if defined(CONFIG_VIDEO_CORALP)
37
38static struct pci_device_id supported[] = {
39 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
40 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
41 { }
42};
43
44
45unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
46#endif
47#endif
48
49#if defined(CONFIG_VIDEO_CORALP)
50#define rd_io in32r
51#define wr_io out32r
52#else
53#define rd_io(addr) in_be32((volatile unsigned *)(addr))
54#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
55#endif
56
57#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
58#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
59 (val))
60#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
61#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
62 (val))
63#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
64#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
65
66#if defined(CONFIG_VIDEO_CORALP)
67#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
68#else
69#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
70#endif
71
72#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
73 (GC_DISP_BASE | GC_L0PAL0) + \
74 ((idx) << 2)), (val))
75
76#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
77static void gdc_sw_reset (void)
78{
79 GraphicDevice *dev = &mb862xx;
80
81 HOST_WR_REG (GC_SRST, 0x1);
82 udelay (500);
83 video_hw_init ();
84}
85
86
87static void de_wait (void)
88{
89 GraphicDevice *dev = &mb862xx;
90 int lc = 0x10000;
91
92
93
94
95
96 while (DE_RD_REG (GC_CTR) & 0x00000131)
97 if (lc-- < 0) {
98 gdc_sw_reset ();
99 puts ("gdc reset done after drawing engine lock.\n");
100 break;
101 }
102}
103
104static void de_wait_slots (int slots)
105{
106 GraphicDevice *dev = &mb862xx;
107 int lc = 0x10000;
108
109
110 while (DE_RD_REG (GC_IFCNT) < slots)
111 if (lc-- < 0) {
112 gdc_sw_reset ();
113 puts ("gdc reset done after drawing engine lock.\n");
114 break;
115 }
116}
117#endif
118
119#if !defined(CONFIG_VIDEO_CORALP)
120static void board_disp_init (void)
121{
122 GraphicDevice *dev = &mb862xx;
123 const gdc_regs *regs = board_get_regs ();
124
125 while (regs->index) {
126 DISP_WR_REG (regs->index, regs->value);
127 regs++;
128 }
129}
130#endif
131
132
133
134
135
136static void de_init (void)
137{
138 GraphicDevice *dev = &mb862xx;
139#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
140 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
141
142 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
143
144
145 de_wait_slots (2);
146 DE_WR_FIFO (0xf1010108);
147 DE_WR_FIFO (cf | 0x0300);
148 DE_WR_REG (GC_FBR, 0x0);
149 DE_WR_REG (GC_XRES, dev->winSizeX);
150 DE_WR_REG (GC_FC, 0x0);
151 DE_WR_REG (GC_BC, 0x0);
152
153 DE_WR_REG (GC_CXMIN, 0x0);
154 DE_WR_REG (GC_CXMAX, dev->winSizeX);
155 DE_WR_REG (GC_CYMIN, 0x0);
156 DE_WR_REG (GC_CYMAX, dev->winSizeY);
157
158
159 de_wait_slots (3);
160 DE_WR_FIFO (0x09410000);
161 DE_WR_FIFO (0x00000000);
162 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
163
164 de_wait ();
165#else
166 unsigned int i, *p;
167
168 i = dev->winSizeX * dev->winSizeY;
169 p = (unsigned int *)dev->frameAdrs;
170 while (i--)
171 *p++ = 0;
172#endif
173}
174
175#if defined(CONFIG_VIDEO_CORALP)
176
177#ifndef CONFIG_SYS_MB862xx_CCF
178#define CONFIG_SYS_MB862xx_CCF 0x00090000
179#endif
180#ifndef CONFIG_SYS_MB862xx_MMR
181#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
182#endif
183
184unsigned int pci_video_init (void)
185{
186 GraphicDevice *dev = &mb862xx;
187 pci_dev_t devbusfn;
188 u16 device;
189
190 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
191 puts("controller not present\n");
192 return 0;
193 }
194
195
196 pci_write_config_dword (devbusfn, PCI_COMMAND,
197 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
198 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
199 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
200
201 if (dev->frameAdrs == 0) {
202 puts ("PCI config: failed to get base address\n");
203 return 0;
204 }
205
206 dev->pciBase = dev->frameAdrs;
207
208 puts("Coral-");
209
210 pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
211 switch (device) {
212 case PCI_DEVICE_ID_CORAL_P:
213 puts("P\n");
214 break;
215 case PCI_DEVICE_ID_CORAL_PA:
216 puts("PA\n");
217 break;
218 default:
219 puts("Unknown\n");
220 return 0;
221 }
222
223
224 HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
225 udelay (200);
226 HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
227 udelay (100);
228 return dev->frameAdrs;
229}
230
231unsigned int card_init (void)
232{
233 GraphicDevice *dev = &mb862xx;
234 unsigned int cf, videomode, div = 0;
235 unsigned long t1, hsync, vsync;
236 char *penv;
237 int tmp, i, bpp;
238 struct ctfb_res_modes *res_mode;
239 struct ctfb_res_modes var_mode;
240
241 memset (dev, 0, sizeof (GraphicDevice));
242
243 if (!pci_video_init ())
244 return 0;
245
246 tmp = 0;
247 videomode = 0x310;
248
249 penv = env_get("videomode");
250 if (penv) {
251
252 if (penv[0] <= '9') {
253 videomode = (int) simple_strtoul (penv, NULL, 16);
254 tmp = 1;
255 }
256 } else {
257 tmp = 1;
258 }
259
260 if (tmp) {
261
262 for (i = 0; i < VESA_MODES_COUNT; i++) {
263 if (vesa_modes[i].vesanr == videomode)
264 break;
265 }
266 if (i == VESA_MODES_COUNT) {
267 printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
268 videomode);
269 i = 0;
270 }
271 res_mode = (struct ctfb_res_modes *)
272 &res_mode_init[vesa_modes[i].resindex];
273 if (vesa_modes[i].resindex > 2) {
274 puts ("\tUnsupported resolution, using default\n");
275 bpp = vesa_modes[1].bits_per_pixel;
276 div = fr_div[1];
277 }
278 bpp = vesa_modes[i].bits_per_pixel;
279 div = fr_div[vesa_modes[i].resindex];
280 } else {
281 res_mode = (struct ctfb_res_modes *) &var_mode;
282 bpp = video_get_params (res_mode, penv);
283 }
284
285
286 t1 = (res_mode->left_margin + res_mode->xres +
287 res_mode->right_margin + res_mode->hsync_len) / 8;
288 t1 *= 8;
289 t1 *= res_mode->pixclock;
290 t1 /= 1000;
291 hsync = 1000000000L / t1;
292 t1 *= (res_mode->upper_margin + res_mode->yres +
293 res_mode->lower_margin + res_mode->vsync_len);
294 t1 /= 1000;
295 vsync = 1000000000L / t1;
296
297
298 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
299 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
300 printf ("\t%s\n", dev->modeIdent);
301 dev->winSizeX = res_mode->xres;
302 dev->winSizeY = res_mode->yres;
303 dev->memSize = VIDEO_MEM_SIZE;
304
305 switch (bpp) {
306 case 8:
307 dev->gdfIndex = GDF__8BIT_INDEX;
308 dev->gdfBytesPP = 1;
309 break;
310 case 15:
311 case 16:
312 dev->gdfIndex = GDF_15BIT_555RGB;
313 dev->gdfBytesPP = 2;
314 break;
315 default:
316 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
317 bpp);
318 puts ("\tfallback to 15bpp\n");
319 dev->gdfIndex = GDF_15BIT_555RGB;
320 dev->gdfBytesPP = 2;
321 }
322
323
324 DISP_WR_REG (GC_DCM1, div);
325
326 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
327 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
328 (dev->winSizeY - 1) | cf);
329 DISP_WR_REG (GC_L0OA0, 0x0);
330 DISP_WR_REG (GC_L0DA0, 0x0);
331 DISP_WR_REG (GC_L0DY_L0DX, 0x0);
332 DISP_WR_REG (GC_L0EM, 0x0);
333 DISP_WR_REG (GC_L0WY_L0WX, 0x0);
334 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
335
336
337 DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
338 res_mode->left_margin +
339 res_mode->right_margin +
340 res_mode->hsync_len - 1) << 16);
341 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
342 (dev->winSizeX - 1));
343 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
344 (res_mode->hsync_len - 1) << 16 |
345 (dev->winSizeX +
346 res_mode->right_margin - 1));
347 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
348 res_mode->upper_margin +
349 res_mode->vsync_len - 1) << 16);
350 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
351 (dev->winSizeY +
352 res_mode->lower_margin - 1));
353 DISP_WR_REG (GC_WY_WX, 0x0);
354 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
355
356 DISP_WR_REG (GC_DCM1, 0x80010000 | div);
357
358 return dev->frameAdrs;
359}
360#endif
361
362
363#if !defined(CONFIG_VIDEO_CORALP)
364int mb862xx_probe(unsigned int addr)
365{
366 GraphicDevice *dev = &mb862xx;
367 unsigned int reg;
368
369 dev->frameAdrs = addr;
370 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
371
372
373 reg = HOST_RD_REG (GC_CID);
374 reg = HOST_RD_REG (GC_CID);
375 if (reg == 0x303) {
376 reg = DE_RD_REG(GC_REV);
377 reg = DE_RD_REG(GC_REV);
378 if ((reg & ~0xff) == 0x20050100)
379 return MB862XX_TYPE_LIME;
380 }
381
382 return 0;
383}
384#endif
385
386void *video_hw_init (void)
387{
388 GraphicDevice *dev = &mb862xx;
389
390 puts ("Video: Fujitsu ");
391
392 memset (dev, 0, sizeof (GraphicDevice));
393
394#if defined(CONFIG_VIDEO_CORALP)
395 if (card_init () == 0)
396 return NULL;
397#else
398
399
400
401
402 if ((dev->frameAdrs = board_video_init ()) == 0) {
403 puts ("Controller not found!\n");
404 return NULL;
405 } else {
406 puts ("Lime\n");
407
408
409 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
410
411 udelay(300);
412
413 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
414 }
415#endif
416
417 de_init ();
418
419#if !defined(CONFIG_VIDEO_CORALP)
420 board_disp_init ();
421#endif
422
423#if (defined(CONFIG_LWMON5) || \
424 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
425
426 board_backlight_switch (1);
427#endif
428
429 return dev;
430}
431
432
433
434
435void video_set_lut (unsigned int index, unsigned char r,
436 unsigned char g, unsigned char b)
437{
438 GraphicDevice *dev = &mb862xx;
439
440 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
441}
442
443#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
444
445
446
447void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
448 unsigned int dst_y, unsigned int dim_x,
449 unsigned int dim_y, unsigned int color)
450{
451 GraphicDevice *dev = &mb862xx;
452
453 de_wait_slots (3);
454 DE_WR_REG (GC_FC, color);
455 DE_WR_FIFO (0x09410000);
456 DE_WR_FIFO ((dst_y << 16) | dst_x);
457 DE_WR_FIFO ((dim_y << 16) | dim_x);
458 de_wait ();
459}
460
461void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
462 unsigned int src_y, unsigned int dst_x,
463 unsigned int dst_y, unsigned int width,
464 unsigned int height)
465{
466 GraphicDevice *dev = &mb862xx;
467 unsigned int ctrl = 0x0d000000L;
468
469 if (src_x >= dst_x && src_y >= dst_y)
470 ctrl |= 0x00440000L;
471 else if (src_x >= dst_x && src_y <= dst_y)
472 ctrl |= 0x00460000L;
473 else if (src_x <= dst_x && src_y >= dst_y)
474 ctrl |= 0x00450000L;
475 else
476 ctrl |= 0x00470000L;
477
478 de_wait_slots (4);
479 DE_WR_FIFO (ctrl);
480 DE_WR_FIFO ((src_y << 16) | src_x);
481 DE_WR_FIFO ((dst_y << 16) | dst_x);
482 DE_WR_FIFO ((height << 16) | width);
483 de_wait ();
484}
485#endif
486
