1/* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __SH7785LCR_H 10#define __SH7785LCR_H 11 12#define CONFIG_CPU_SH7785 1 13#define CONFIG_SH7785LCR 1 14 15#define CONFIG_EXTRA_ENV_SETTINGS \ 16 "bootdevice=0:1\0" \ 17 "usbload=usb reset;usbboot;usb stop;bootm\0" 18 19#define CONFIG_DISPLAY_BOARDINFO 20#undef CONFIG_SHOW_BOOT_PROGRESS 21 22/* MEMORY */ 23#if defined(CONFIG_SH_32BIT) 24#define CONFIG_SYS_TEXT_BASE 0x8FF80000 25/* 0x40000000 - 0x47FFFFFF does not use */ 26#define CONFIG_SH_SDRAM_OFFSET (0x8000000) 27#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 28#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 29#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 30#define SH7785LCR_FLASH_BASE_1 (0xa0000000) 31#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 32#define SH7785LCR_USB_BASE (0xa6000000) 33#else 34#define CONFIG_SYS_TEXT_BASE 0x0FF80000 35#define SH7785LCR_SDRAM_BASE (0x08000000) 36#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 37#define SH7785LCR_FLASH_BASE_1 (0xa0000000) 38#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 39#define SH7785LCR_USB_BASE (0xb4000000) 40#endif 41 42#define CONFIG_SYS_LONGHELP 43#define CONFIG_SYS_PBSIZE 256 44#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 45 46/* SCIF */ 47#define CONFIG_CONS_SCIF1 1 48#define CONFIG_SCIF_EXT_CLOCK 1 49 50#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 51#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 52 (SH7785LCR_SDRAM_SIZE) - \ 53 4 * 1024 * 1024) 54#undef CONFIG_SYS_ALT_MEMTEST 55#undef CONFIG_SYS_MEMTEST_SCRATCH 56#undef CONFIG_SYS_LOADS_BAUD_CHANGE 57 58#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 59#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 60#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 61 62#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 63#define CONFIG_SYS_MONITOR_LEN (512 * 1024) 64#define CONFIG_SYS_MALLOC_LEN (512 * 1024) 65#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 66 67/* FLASH */ 68#define CONFIG_FLASH_CFI_DRIVER 69#define CONFIG_SYS_FLASH_CFI 70#undef CONFIG_SYS_FLASH_QUIET_TEST 71#define CONFIG_SYS_FLASH_EMPTY_INFO 72#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 73#define CONFIG_SYS_MAX_FLASH_SECT 512 74 75#define CONFIG_SYS_MAX_FLASH_BANKS 1 76#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 77 (0 * SH7785LCR_FLASH_BANK_SIZE) } 78 79#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 80#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 81#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 82#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 83 84#undef CONFIG_SYS_FLASH_PROTECTION 85#undef CONFIG_SYS_DIRECT_FLASH_TFTP 86 87/* R8A66597 */ 88#define CONFIG_USB_R8A66597_HCD 89#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 90#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 91#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 92#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 93 94/* PCI Controller */ 95#define CONFIG_SH4_PCI 96#define CONFIG_SH7780_PCI 97#if defined(CONFIG_SH_32BIT) 98#define CONFIG_SH7780_PCI_LSR 0x1ff00001 99#define CONFIG_SH7780_PCI_LAR 0x5f000000 100#define CONFIG_SH7780_PCI_BAR 0x5f000000 101#else 102#define CONFIG_SH7780_PCI_LSR 0x07f00001 103#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 104#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 105#endif 106#define CONFIG_PCI_SCAN_SHOW 1 107 108#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 109#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 110#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 111 112#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 113#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 114#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 115 116#if defined(CONFIG_SH_32BIT) 117#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 118#else 119#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 120#endif 121#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 122#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 123 124/* ENV setting */ 125#define CONFIG_ENV_OVERWRITE 1 126#define CONFIG_ENV_SECT_SIZE (256 * 1024) 127#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 128#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 129#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 130#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 131 132/* Board Clock */ 133/* The SCIF used external clock. system clock only used timer. */ 134#define CONFIG_SYS_CLK_FREQ 50000000 135#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 136#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 137#define CONFIG_SYS_TMU_CLK_DIV 4 138 139#endif /* __SH7785LCR_H */ 140