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11#ifndef _PCI_H
12#define _PCI_H
13
14#define PCI_CFG_SPACE_SIZE 256
15#define PCI_CFG_SPACE_EXP_SIZE 4096
16
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20
21#define PCI_VENDOR_ID 0x00
22#define PCI_DEVICE_ID 0x02
23#define PCI_COMMAND 0x04
24#define PCI_COMMAND_IO 0x1
25#define PCI_COMMAND_MEMORY 0x2
26#define PCI_COMMAND_MASTER 0x4
27#define PCI_COMMAND_SPECIAL 0x8
28#define PCI_COMMAND_INVALIDATE 0x10
29#define PCI_COMMAND_VGA_PALETTE 0x20
30#define PCI_COMMAND_PARITY 0x40
31#define PCI_COMMAND_WAIT 0x80
32#define PCI_COMMAND_SERR 0x100
33#define PCI_COMMAND_FAST_BACK 0x200
34
35#define PCI_STATUS 0x06
36#define PCI_STATUS_CAP_LIST 0x10
37#define PCI_STATUS_66MHZ 0x20
38#define PCI_STATUS_UDF 0x40
39#define PCI_STATUS_FAST_BACK 0x80
40#define PCI_STATUS_PARITY 0x100
41#define PCI_STATUS_DEVSEL_MASK 0x600
42#define PCI_STATUS_DEVSEL_FAST 0x000
43#define PCI_STATUS_DEVSEL_MEDIUM 0x200
44#define PCI_STATUS_DEVSEL_SLOW 0x400
45#define PCI_STATUS_SIG_TARGET_ABORT 0x800
46#define PCI_STATUS_REC_TARGET_ABORT 0x1000
47#define PCI_STATUS_REC_MASTER_ABORT 0x2000
48#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
49#define PCI_STATUS_DETECTED_PARITY 0x8000
50
51#define PCI_CLASS_REVISION 0x08
52
53#define PCI_REVISION_ID 0x08
54#define PCI_CLASS_PROG 0x09
55#define PCI_CLASS_DEVICE 0x0a
56#define PCI_CLASS_CODE 0x0b
57#define PCI_CLASS_CODE_TOO_OLD 0x00
58#define PCI_CLASS_CODE_STORAGE 0x01
59#define PCI_CLASS_CODE_NETWORK 0x02
60#define PCI_CLASS_CODE_DISPLAY 0x03
61#define PCI_CLASS_CODE_MULTIMEDIA 0x04
62#define PCI_CLASS_CODE_MEMORY 0x05
63#define PCI_CLASS_CODE_BRIDGE 0x06
64#define PCI_CLASS_CODE_COMM 0x07
65#define PCI_CLASS_CODE_PERIPHERAL 0x08
66#define PCI_CLASS_CODE_INPUT 0x09
67#define PCI_CLASS_CODE_DOCKING 0x0A
68#define PCI_CLASS_CODE_PROCESSOR 0x0B
69#define PCI_CLASS_CODE_SERIAL 0x0C
70#define PCI_CLASS_CODE_WIRELESS 0x0D
71#define PCI_CLASS_CODE_I2O 0x0E
72#define PCI_CLASS_CODE_SATELLITE 0x0F
73#define PCI_CLASS_CODE_CRYPTO 0x10
74#define PCI_CLASS_CODE_DATA 0x11
75
76#define PCI_CLASS_CODE_OTHER 0xFF
77
78#define PCI_CLASS_SUB_CODE 0x0a
79#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
181
182#define PCI_CACHE_LINE_SIZE 0x0c
183#define PCI_LATENCY_TIMER 0x0d
184#define PCI_HEADER_TYPE 0x0e
185#define PCI_HEADER_TYPE_NORMAL 0
186#define PCI_HEADER_TYPE_BRIDGE 1
187#define PCI_HEADER_TYPE_CARDBUS 2
188
189#define PCI_BIST 0x0f
190#define PCI_BIST_CODE_MASK 0x0f
191#define PCI_BIST_START 0x40
192#define PCI_BIST_CAPABLE 0x80
193
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198
199
200#define PCI_BASE_ADDRESS_0 0x10
201#define PCI_BASE_ADDRESS_1 0x14
202#define PCI_BASE_ADDRESS_2 0x18
203#define PCI_BASE_ADDRESS_3 0x1c
204#define PCI_BASE_ADDRESS_4 0x20
205#define PCI_BASE_ADDRESS_5 0x24
206#define PCI_BASE_ADDRESS_SPACE 0x01
207#define PCI_BASE_ADDRESS_SPACE_IO 0x01
208#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
211#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
212#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
213#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
214#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
216
217
218
219#define PCI_CARDBUS_CIS 0x28
220#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
221#define PCI_SUBSYSTEM_ID 0x2e
222#define PCI_ROM_ADDRESS 0x30
223#define PCI_ROM_ADDRESS_ENABLE 0x01
224#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
225
226#define PCI_CAPABILITY_LIST 0x34
227
228
229#define PCI_INTERRUPT_LINE 0x3c
230#define PCI_INTERRUPT_PIN 0x3d
231#define PCI_MIN_GNT 0x3e
232#define PCI_MAX_LAT 0x3f
233
234#define PCI_INTERRUPT_LINE_DISABLE 0xff
235
236
237#define PCI_PRIMARY_BUS 0x18
238#define PCI_SECONDARY_BUS 0x19
239#define PCI_SUBORDINATE_BUS 0x1a
240#define PCI_SEC_LATENCY_TIMER 0x1b
241#define PCI_IO_BASE 0x1c
242#define PCI_IO_LIMIT 0x1d
243#define PCI_IO_RANGE_TYPE_MASK 0x0f
244#define PCI_IO_RANGE_TYPE_16 0x00
245#define PCI_IO_RANGE_TYPE_32 0x01
246#define PCI_IO_RANGE_MASK ~0x0f
247#define PCI_SEC_STATUS 0x1e
248#define PCI_MEMORY_BASE 0x20
249#define PCI_MEMORY_LIMIT 0x22
250#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
251#define PCI_MEMORY_RANGE_MASK ~0x0f
252#define PCI_PREF_MEMORY_BASE 0x24
253#define PCI_PREF_MEMORY_LIMIT 0x26
254#define PCI_PREF_RANGE_TYPE_MASK 0x0f
255#define PCI_PREF_RANGE_TYPE_32 0x00
256#define PCI_PREF_RANGE_TYPE_64 0x01
257#define PCI_PREF_RANGE_MASK ~0x0f
258#define PCI_PREF_BASE_UPPER32 0x28
259#define PCI_PREF_LIMIT_UPPER32 0x2c
260#define PCI_IO_BASE_UPPER16 0x30
261#define PCI_IO_LIMIT_UPPER16 0x32
262
263
264#define PCI_ROM_ADDRESS1 0x38
265
266#define PCI_BRIDGE_CONTROL 0x3e
267#define PCI_BRIDGE_CTL_PARITY 0x01
268#define PCI_BRIDGE_CTL_SERR 0x02
269#define PCI_BRIDGE_CTL_NO_ISA 0x04
270#define PCI_BRIDGE_CTL_VGA 0x08
271#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
272#define PCI_BRIDGE_CTL_BUS_RESET 0x40
273#define PCI_BRIDGE_CTL_FAST_BACK 0x80
274
275
276#define PCI_ERREN 0x48
277#define PCI_ERRSTS 0x49
278#define PCI_BRDGOPT1 0x4A
279#define PCI_PLBSESR0 0x4C
280#define PCI_PLBSESR1 0x50
281#define PCI_PLBSEAR 0x54
282#define PCI_CAPID 0x58
283#define PCI_NEXTITEMPTR 0x59
284#define PCI_PMC 0x5A
285#define PCI_PMCSR 0x5C
286#define PCI_PMCSRBSE 0x5E
287#define PCI_BRDGOPT2 0x60
288#define PCI_PMSCRR 0x64
289
290
291#define PCI_CB_CAPABILITY_LIST 0x14
292
293#define PCI_CB_SEC_STATUS 0x16
294#define PCI_CB_PRIMARY_BUS 0x18
295#define PCI_CB_CARD_BUS 0x19
296#define PCI_CB_SUBORDINATE_BUS 0x1a
297#define PCI_CB_LATENCY_TIMER 0x1b
298#define PCI_CB_MEMORY_BASE_0 0x1c
299#define PCI_CB_MEMORY_LIMIT_0 0x20
300#define PCI_CB_MEMORY_BASE_1 0x24
301#define PCI_CB_MEMORY_LIMIT_1 0x28
302#define PCI_CB_IO_BASE_0 0x2c
303#define PCI_CB_IO_BASE_0_HI 0x2e
304#define PCI_CB_IO_LIMIT_0 0x30
305#define PCI_CB_IO_LIMIT_0_HI 0x32
306#define PCI_CB_IO_BASE_1 0x34
307#define PCI_CB_IO_BASE_1_HI 0x36
308#define PCI_CB_IO_LIMIT_1 0x38
309#define PCI_CB_IO_LIMIT_1_HI 0x3a
310#define PCI_CB_IO_RANGE_MASK ~0x03
311
312#define PCI_CB_BRIDGE_CONTROL 0x3e
313#define PCI_CB_BRIDGE_CTL_PARITY 0x01
314#define PCI_CB_BRIDGE_CTL_SERR 0x02
315#define PCI_CB_BRIDGE_CTL_ISA 0x04
316#define PCI_CB_BRIDGE_CTL_VGA 0x08
317#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
318#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
319#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
320#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
321#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
322#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
323#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
324#define PCI_CB_SUBSYSTEM_ID 0x42
325#define PCI_CB_LEGACY_MODE_BASE 0x44
326
327
328
329
330#define PCI_CAP_LIST_ID 0
331#define PCI_CAP_ID_PM 0x01
332#define PCI_CAP_ID_AGP 0x02
333#define PCI_CAP_ID_VPD 0x03
334#define PCI_CAP_ID_SLOTID 0x04
335#define PCI_CAP_ID_MSI 0x05
336#define PCI_CAP_ID_CHSWP 0x06
337#define PCI_CAP_ID_EXP 0x10
338#define PCI_CAP_LIST_NEXT 1
339#define PCI_CAP_FLAGS 2
340#define PCI_CAP_SIZEOF 4
341
342
343
344#define PCI_PM_CAP_VER_MASK 0x0007
345#define PCI_PM_CAP_PME_CLOCK 0x0008
346#define PCI_PM_CAP_AUX_POWER 0x0010
347#define PCI_PM_CAP_DSI 0x0020
348#define PCI_PM_CAP_D1 0x0200
349#define PCI_PM_CAP_D2 0x0400
350#define PCI_PM_CAP_PME 0x0800
351#define PCI_PM_CTRL 4
352#define PCI_PM_CTRL_STATE_MASK 0x0003
353#define PCI_PM_CTRL_PME_ENABLE 0x0100
354#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
355#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
356#define PCI_PM_CTRL_PME_STATUS 0x8000
357#define PCI_PM_PPB_EXTENSIONS 6
358#define PCI_PM_PPB_B2_B3 0x40
359#define PCI_PM_BPCC_ENABLE 0x80
360#define PCI_PM_DATA_REGISTER 7
361#define PCI_PM_SIZEOF 8
362
363
364
365#define PCI_AGP_VERSION 2
366#define PCI_AGP_RFU 3
367#define PCI_AGP_STATUS 4
368#define PCI_AGP_STATUS_RQ_MASK 0xff000000
369#define PCI_AGP_STATUS_SBA 0x0200
370#define PCI_AGP_STATUS_64BIT 0x0020
371#define PCI_AGP_STATUS_FW 0x0010
372#define PCI_AGP_STATUS_RATE4 0x0004
373#define PCI_AGP_STATUS_RATE2 0x0002
374#define PCI_AGP_STATUS_RATE1 0x0001
375#define PCI_AGP_COMMAND 8
376#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
377#define PCI_AGP_COMMAND_SBA 0x0200
378#define PCI_AGP_COMMAND_AGP 0x0100
379#define PCI_AGP_COMMAND_64BIT 0x0020
380#define PCI_AGP_COMMAND_FW 0x0010
381#define PCI_AGP_COMMAND_RATE4 0x0004
382#define PCI_AGP_COMMAND_RATE2 0x0002
383#define PCI_AGP_COMMAND_RATE1 0x0001
384#define PCI_AGP_SIZEOF 12
385
386
387
388#define PCI_X_CMD_DPERR_E 0x0001
389#define PCI_X_CMD_ERO 0x0002
390#define PCI_X_CMD_MAX_READ 0x0000
391#define PCI_X_CMD_MAX_SPLIT 0x0030
392#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
393
394
395
396
397#define PCI_SID_ESR 2
398#define PCI_SID_ESR_NSLOTS 0x1f
399#define PCI_SID_ESR_FIC 0x20
400#define PCI_SID_CHASSIS_NR 3
401
402
403
404#define PCI_MSI_FLAGS 2
405#define PCI_MSI_FLAGS_64BIT 0x80
406#define PCI_MSI_FLAGS_QSIZE 0x70
407#define PCI_MSI_FLAGS_QMASK 0x0e
408#define PCI_MSI_FLAGS_ENABLE 0x01
409#define PCI_MSI_RFU 3
410#define PCI_MSI_ADDRESS_LO 4
411#define PCI_MSI_ADDRESS_HI 8
412#define PCI_MSI_DATA_32 8
413#define PCI_MSI_DATA_64 12
414
415#define PCI_MAX_PCI_DEVICES 32
416#define PCI_MAX_PCI_FUNCTIONS 8
417
418#define PCI_FIND_CAP_TTL 0x48
419#define CAP_START_POS 0x40
420
421
422#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
423#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
424#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
425
426#define PCI_EXT_CAP_ID_ERR 0x01
427#define PCI_EXT_CAP_ID_VC 0x02
428#define PCI_EXT_CAP_ID_DSN 0x03
429#define PCI_EXT_CAP_ID_PWR 0x04
430#define PCI_EXT_CAP_ID_RCLD 0x05
431#define PCI_EXT_CAP_ID_RCILC 0x06
432#define PCI_EXT_CAP_ID_RCEC 0x07
433#define PCI_EXT_CAP_ID_MFVC 0x08
434#define PCI_EXT_CAP_ID_VC9 0x09
435#define PCI_EXT_CAP_ID_RCRB 0x0A
436#define PCI_EXT_CAP_ID_VNDR 0x0B
437#define PCI_EXT_CAP_ID_CAC 0x0C
438#define PCI_EXT_CAP_ID_ACS 0x0D
439#define PCI_EXT_CAP_ID_ARI 0x0E
440#define PCI_EXT_CAP_ID_ATS 0x0F
441#define PCI_EXT_CAP_ID_SRIOV 0x10
442#define PCI_EXT_CAP_ID_MRIOV 0x11
443#define PCI_EXT_CAP_ID_MCAST 0x12
444#define PCI_EXT_CAP_ID_PRI 0x13
445#define PCI_EXT_CAP_ID_AMD_XXX 0x14
446#define PCI_EXT_CAP_ID_REBAR 0x15
447#define PCI_EXT_CAP_ID_DPA 0x16
448#define PCI_EXT_CAP_ID_TPH 0x17
449#define PCI_EXT_CAP_ID_LTR 0x18
450#define PCI_EXT_CAP_ID_SECPCI 0x19
451#define PCI_EXT_CAP_ID_PMUX 0x1A
452#define PCI_EXT_CAP_ID_PASID 0x1B
453
454
455
456#include <pci_ids.h>
457
458#ifndef __ASSEMBLY__
459
460#ifdef CONFIG_SYS_PCI_64BIT
461typedef u64 pci_addr_t;
462typedef u64 pci_size_t;
463#else
464typedef u32 pci_addr_t;
465typedef u32 pci_size_t;
466#endif
467
468struct pci_region {
469 pci_addr_t bus_start;
470 phys_addr_t phys_start;
471 pci_size_t size;
472 unsigned long flags;
473
474 pci_addr_t bus_lower;
475};
476
477#define PCI_REGION_MEM 0x00000000
478#define PCI_REGION_IO 0x00000001
479#define PCI_REGION_TYPE 0x00000001
480#define PCI_REGION_PREFETCH 0x00000008
481
482#define PCI_REGION_SYS_MEMORY 0x00000100
483#define PCI_REGION_RO 0x00000200
484
485static inline void pci_set_region(struct pci_region *reg,
486 pci_addr_t bus_start,
487 phys_addr_t phys_start,
488 pci_size_t size,
489 unsigned long flags) {
490 reg->bus_start = bus_start;
491 reg->phys_start = phys_start;
492 reg->size = size;
493 reg->flags = flags;
494}
495
496typedef int pci_dev_t;
497
498#define PCI_BUS(d) (((d) >> 16) & 0xff)
499#define PCI_DEV(d) (((d) >> 11) & 0x1f)
500#define PCI_FUNC(d) (((d) >> 8) & 0x7)
501#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
502#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
503#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
504#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
505#define PCI_VENDEV(v, d) (((v) << 16) | (d))
506#define PCI_ANY_ID (~0)
507
508struct pci_device_id {
509 unsigned int vendor, device;
510 unsigned int subvendor, subdevice;
511 unsigned int class, class_mask;
512 unsigned long driver_data;
513};
514
515struct pci_controller;
516
517struct pci_config_table {
518 unsigned int vendor, device;
519 unsigned int class;
520 unsigned int bus;
521 unsigned int dev;
522 unsigned int func;
523
524 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
525 struct pci_config_table *);
526 unsigned long priv[3];
527};
528
529extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
530 struct pci_config_table *);
531extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
532 struct pci_config_table *);
533
534#define MAX_PCI_REGIONS 7
535
536#define INDIRECT_TYPE_NO_PCIE_LINK 1
537
538
539
540
541
542
543struct pci_controller {
544#ifdef CONFIG_DM_PCI
545 struct udevice *bus;
546 struct udevice *ctlr;
547#else
548 struct pci_controller *next;
549#endif
550
551 int first_busno;
552 int last_busno;
553
554 volatile unsigned int *cfg_addr;
555 volatile unsigned char *cfg_data;
556
557 int indirect_type;
558
559
560
561
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568
569 struct pci_region regions[MAX_PCI_REGIONS];
570 int region_count;
571
572 struct pci_config_table *config_table;
573
574 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
575#ifndef CONFIG_DM_PCI
576
577 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
578 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
579 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
580 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
581 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
582 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
583#endif
584
585
586 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
587
588
589 struct pci_region *pci_fb;
590#ifndef CONFIG_DM_PCI
591 int current_busno;
592
593 void *priv_data;
594#endif
595};
596
597#ifndef CONFIG_DM_PCI
598static inline void pci_set_ops(struct pci_controller *hose,
599 int (*read_byte)(struct pci_controller*,
600 pci_dev_t, int where, u8 *),
601 int (*read_word)(struct pci_controller*,
602 pci_dev_t, int where, u16 *),
603 int (*read_dword)(struct pci_controller*,
604 pci_dev_t, int where, u32 *),
605 int (*write_byte)(struct pci_controller*,
606 pci_dev_t, int where, u8),
607 int (*write_word)(struct pci_controller*,
608 pci_dev_t, int where, u16),
609 int (*write_dword)(struct pci_controller*,
610 pci_dev_t, int where, u32)) {
611 hose->read_byte = read_byte;
612 hose->read_word = read_word;
613 hose->read_dword = read_dword;
614 hose->write_byte = write_byte;
615 hose->write_word = write_word;
616 hose->write_dword = write_dword;
617}
618#endif
619
620#ifdef CONFIG_PCI_INDIRECT_BRIDGE
621extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
622#endif
623
624#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
625extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
626 pci_addr_t addr, unsigned long flags);
627extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
628 phys_addr_t addr, unsigned long flags);
629
630#define pci_phys_to_bus(dev, addr, flags) \
631 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
632#define pci_bus_to_phys(dev, addr, flags) \
633 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
634
635#define pci_virt_to_bus(dev, addr, flags) \
636 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
637 (virt_to_phys(addr)), (flags))
638#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
639 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
640 (addr), (flags)), \
641 (len), (map_flags))
642
643#define pci_phys_to_mem(dev, addr) \
644 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
645#define pci_mem_to_phys(dev, addr) \
646 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
647#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
648#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
649
650#define pci_virt_to_mem(dev, addr) \
651 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
652#define pci_mem_to_virt(dev, addr, len, map_flags) \
653 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
654#define pci_virt_to_io(dev, addr) \
655 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
656#define pci_io_to_virt(dev, addr, len, map_flags) \
657 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
658
659
660extern int pci_hose_read_config_byte(struct pci_controller *hose,
661 pci_dev_t dev, int where, u8 *val);
662extern int pci_hose_read_config_word(struct pci_controller *hose,
663 pci_dev_t dev, int where, u16 *val);
664extern int pci_hose_read_config_dword(struct pci_controller *hose,
665 pci_dev_t dev, int where, u32 *val);
666extern int pci_hose_write_config_byte(struct pci_controller *hose,
667 pci_dev_t dev, int where, u8 val);
668extern int pci_hose_write_config_word(struct pci_controller *hose,
669 pci_dev_t dev, int where, u16 val);
670extern int pci_hose_write_config_dword(struct pci_controller *hose,
671 pci_dev_t dev, int where, u32 val);
672#endif
673
674#ifndef CONFIG_DM_PCI
675extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
676extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
677extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
678extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
679extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
680extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
681#endif
682
683void pciauto_region_init(struct pci_region *res);
684void pciauto_region_align(struct pci_region *res, pci_size_t size);
685void pciauto_config_init(struct pci_controller *hose);
686int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
687 pci_addr_t *bar);
688
689#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
690extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
691 pci_dev_t dev, int where, u8 *val);
692extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
693 pci_dev_t dev, int where, u16 *val);
694extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
695 pci_dev_t dev, int where, u8 val);
696extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
697 pci_dev_t dev, int where, u16 val);
698
699extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
700extern void pci_register_hose(struct pci_controller* hose);
701extern struct pci_controller* pci_bus_to_hose(int bus);
702extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
703extern struct pci_controller *pci_get_hose_head(void);
704
705extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
706extern int pci_hose_scan(struct pci_controller *hose);
707extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
708
709extern void pciauto_setup_device(struct pci_controller *hose,
710 pci_dev_t dev, int bars_num,
711 struct pci_region *mem,
712 struct pci_region *prefetch,
713 struct pci_region *io);
714extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
715 pci_dev_t dev, int sub_bus);
716extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
717 pci_dev_t dev, int sub_bus);
718extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
719
720extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
721extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
722pci_dev_t pci_find_class(unsigned int find_class, int index);
723
724extern int pci_hose_config_device(struct pci_controller *hose,
725 pci_dev_t dev,
726 unsigned long io,
727 pci_addr_t mem,
728 unsigned long command);
729
730extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
731 int cap);
732extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
733 u8 hdr_type);
734extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
735 int cap);
736
737int pci_find_next_ext_capability(struct pci_controller *hose,
738 pci_dev_t dev, int start, int cap);
739int pci_hose_find_ext_capability(struct pci_controller *hose,
740 pci_dev_t dev, int cap);
741
742#ifdef CONFIG_PCI_FIXUP_DEV
743extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
744 unsigned short vendor,
745 unsigned short device,
746 unsigned short class);
747#endif
748#endif
749
750const char * pci_class_str(u8 class);
751int pci_last_busno(void);
752
753#ifdef CONFIG_MPC85xx
754extern void pci_mpc85xx_init (struct pci_controller *hose);
755#endif
756
757#ifdef CONFIG_PCIE_IMX
758extern void imx_pcie_remove(void);
759#endif
760
761#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
762
763
764
765
766
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769
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773
774void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
775 u32 addr);
776
777
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779
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784
785u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
786
787
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795
796
797
798pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
799 struct pci_device_id *ids, int *indexp);
800#endif
801
802
803enum pci_size_t {
804 PCI_SIZE_8,
805 PCI_SIZE_16,
806 PCI_SIZE_32,
807};
808
809struct udevice;
810
811#ifdef CONFIG_DM_PCI
812
813
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815
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819
820
821
822
823
824
825struct pci_child_platdata {
826 int devfn;
827 unsigned short vendor;
828 unsigned short device;
829 unsigned int class;
830};
831
832
833struct dm_pci_ops {
834
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851
852 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
853 ulong *valuep, enum pci_size_t size);
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863
864 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
865 ulong value, enum pci_size_t size);
866};
867
868
869#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
870
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876
877pci_dev_t dm_pci_get_bdf(struct udevice *dev);
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894int pci_bind_bus_devices(struct udevice *bus);
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909int pci_auto_config_devices(struct udevice *bus);
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917
918int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
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926
927int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
928 struct udevice **devp);
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941int pci_find_first_device(struct udevice **devp);
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953int pci_find_next_device(struct udevice **devp);
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961
962int pci_get_ff(enum pci_size_t size);
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976int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
977 int *indexp, struct udevice **devp);
978
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988int pci_find_device_id(struct pci_device_id *ids, int index,
989 struct udevice **devp);
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1005int dm_pci_hose_probe_bus(struct udevice *bus);
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1020int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1021 unsigned long *valuep, enum pci_size_t size);
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1033int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1034 unsigned long value, enum pci_size_t size);
1035
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1047
1048int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1049 u32 clr, u32 set);
1050
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1054
1055int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1056 enum pci_size_t size);
1057
1058int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1059int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1060int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1061
1062int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1063 enum pci_size_t size);
1064
1065int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1066int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1067int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
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1072
1073int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1074int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1075int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
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1081
1082int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1083int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1084int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1085int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1086int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1087int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
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1107int pci_generic_mmap_write_config(
1108 struct udevice *bus,
1109 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1110 pci_dev_t bdf,
1111 uint offset,
1112 ulong value,
1113 enum pci_size_t size);
1114
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1132int pci_generic_mmap_read_config(
1133 struct udevice *bus,
1134 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1135 pci_dev_t bdf,
1136 uint offset,
1137 ulong *valuep,
1138 enum pci_size_t size);
1139
1140#ifdef CONFIG_DM_PCI_COMPAT
1141
1142static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1143 u32 value)
1144{
1145 return pci_write_config32(pcidev, offset, value);
1146}
1147
1148
1149static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1150 u16 value)
1151{
1152 return pci_write_config16(pcidev, offset, value);
1153}
1154
1155
1156static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1157 u8 value)
1158{
1159 return pci_write_config8(pcidev, offset, value);
1160}
1161
1162
1163static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1164 u32 *valuep)
1165{
1166 return pci_read_config32(pcidev, offset, valuep);
1167}
1168
1169
1170static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1171 u16 *valuep)
1172{
1173 return pci_read_config16(pcidev, offset, valuep);
1174}
1175
1176
1177static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1178 u8 *valuep)
1179{
1180 return pci_read_config8(pcidev, offset, valuep);
1181}
1182#endif
1183
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1190
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1192
1193int dm_pciauto_config_device(struct udevice *dev);
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1207
1208ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
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1222
1223ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1224 enum pci_size_t size);
1225
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1229
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1231
1232struct udevice *pci_get_controller(struct udevice *dev);
1233
1234
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1241
1242
1243int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1244 struct pci_region **memp, struct pci_region **prefp);
1245
1246
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1254
1255void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1256
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1264u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
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1273
1274phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1275 unsigned long flags);
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1285pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1286 unsigned long flags);
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1298
1299void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1300
1301#define dm_pci_virt_to_bus(dev, addr, flags) \
1302 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1303#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1304 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1305 (len), (map_flags))
1306
1307#define dm_pci_phys_to_mem(dev, addr) \
1308 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1309#define dm_pci_mem_to_phys(dev, addr) \
1310 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1311#define dm_pci_phys_to_io(dev, addr) \
1312 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1313#define dm_pci_io_to_phys(dev, addr) \
1314 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1315
1316#define dm_pci_virt_to_mem(dev, addr) \
1317 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1318#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1319 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1320#define dm_pci_virt_to_io(dev, addr) \
1321 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1322#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1323 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1324
1325
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1333
1334int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1335 struct udevice **devp);
1336
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1343
1344
1345int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1346
1347
1348
1349
1350struct dm_pci_emul_ops {
1351
1352
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1356
1357 int (*get_devfn)(struct udevice *dev);
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1366
1367 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1368 enum pci_size_t size);
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1377
1378 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1379 enum pci_size_t size);
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1390 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1391 enum pci_size_t size);
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1400
1401
1402 int (*write_io)(struct udevice *dev, unsigned int addr,
1403 ulong value, enum pci_size_t size);
1404
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1407
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1409
1410
1411
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1418
1419 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1420 unsigned long *lenp, void **ptrp);
1421
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1434
1435 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1436 unsigned long len);
1437};
1438
1439
1440#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1441
1442
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1448
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1451
1452int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1453 struct udevice **emulp);
1454
1455#endif
1456
1457
1458
1459
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1465
1466#define PCI_DEVICE(vend, dev) \
1467 .vendor = (vend), .device = (dev), \
1468 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1469
1470
1471
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1479
1480#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1481 .vendor = (vend), .device = (dev), \
1482 .subvendor = (subvend), .subdevice = (subdev)
1483
1484
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1491
1492
1493#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1494 .class = (dev_class), .class_mask = (dev_class_mask), \
1495 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1496 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1497
1498
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1500
1501
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1508
1509#define PCI_VDEVICE(vend, dev) \
1510 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1511 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1512
1513
1514
1515
1516
1517
1518struct pci_driver_entry {
1519 struct driver *driver;
1520 const struct pci_device_id *match;
1521};
1522
1523#define U_BOOT_PCI_DEVICE(__name, __match) \
1524 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1525 .driver = llsym(struct driver, __name, driver), \
1526 .match = __match, \
1527 }
1528
1529#endif
1530#endif
1531