LXR uboot/include/phy.h

   1/*
   2 * Copyright 2011 Freescale Semiconductor, Inc.
   3 *      Andy Fleming <afleming@gmail.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 *
   7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   8 */
   9
  10#ifndef _PHY_H
  11#define _PHY_H
  12
  13#include <linux/list.h>
  14#include <linux/mii.h>
  15#include <linux/ethtool.h>
  16#include <linux/mdio.h>
  17
  18#define PHY_FIXED_ID            0xa5a55a5a
  19/*
  20 * There is no actual id for this.
  21 * This is just a dummy id for gmii2rgmmi converter
  22 */
  23#define PHY_GMII2RGMII_ID       0x5a5a5a5a
  24
  25#define PHY_MAX_ADDR 32
  26
  27#define PHY_FLAG_BROKEN_RESET   (1 << 0) /* soft reset not supported */
  28
  29#define PHY_DEFAULT_FEATURES    (SUPPORTED_Autoneg | \
  30                                 SUPPORTED_TP | \
  31                                 SUPPORTED_MII)
  32
  33#define PHY_10BT_FEATURES       (SUPPORTED_10baseT_Half | \
  34                                 SUPPORTED_10baseT_Full)
  35
  36#define PHY_100BT_FEATURES      (SUPPORTED_100baseT_Half | \
  37                                 SUPPORTED_100baseT_Full)
  38
  39#define PHY_1000BT_FEATURES     (SUPPORTED_1000baseT_Half | \
  40                                 SUPPORTED_1000baseT_Full)
  41
  42#define PHY_BASIC_FEATURES      (PHY_10BT_FEATURES | \
  43                                 PHY_100BT_FEATURES | \
  44                                 PHY_DEFAULT_FEATURES)
  45
  46#define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
  47                                 PHY_1000BT_FEATURES)
  48
  49#define PHY_10G_FEATURES        (PHY_GBIT_FEATURES | \
  50                                SUPPORTED_10000baseT_Full)
  51
  52#ifndef PHY_ANEG_TIMEOUT
  53#define PHY_ANEG_TIMEOUT        4000
  54#endif
  55
  56
  57typedef enum {
  58        PHY_INTERFACE_MODE_MII,
  59        PHY_INTERFACE_MODE_GMII,
  60        PHY_INTERFACE_MODE_SGMII,
  61        PHY_INTERFACE_MODE_SGMII_2500,
  62        PHY_INTERFACE_MODE_QSGMII,
  63        PHY_INTERFACE_MODE_TBI,
  64        PHY_INTERFACE_MODE_RMII,
  65        PHY_INTERFACE_MODE_RGMII,
  66        PHY_INTERFACE_MODE_RGMII_ID,
  67        PHY_INTERFACE_MODE_RGMII_RXID,
  68        PHY_INTERFACE_MODE_RGMII_TXID,
  69        PHY_INTERFACE_MODE_RTBI,
  70        PHY_INTERFACE_MODE_XGMII,
  71        PHY_INTERFACE_MODE_XAUI,
  72        PHY_INTERFACE_MODE_RXAUI,
  73        PHY_INTERFACE_MODE_SFI,
  74        PHY_INTERFACE_MODE_NONE,        /* Must be last */
  75
  76        PHY_INTERFACE_MODE_COUNT,
  77} phy_interface_t;
  78
  79static const char *phy_interface_strings[] = {
  80        [PHY_INTERFACE_MODE_MII]                = "mii",
  81        [PHY_INTERFACE_MODE_GMII]               = "gmii",
  82        [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
  83        [PHY_INTERFACE_MODE_SGMII_2500]         = "sgmii-2500",
  84        [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
  85        [PHY_INTERFACE_MODE_TBI]                = "tbi",
  86        [PHY_INTERFACE_MODE_RMII]               = "rmii",
  87        [PHY_INTERFACE_MODE_RGMII]              = "rgmii",
  88        [PHY_INTERFACE_MODE_RGMII_ID]           = "rgmii-id",
  89        [PHY_INTERFACE_MODE_RGMII_RXID]         = "rgmii-rxid",
  90        [PHY_INTERFACE_MODE_RGMII_TXID]         = "rgmii-txid",
  91        [PHY_INTERFACE_MODE_RTBI]               = "rtbi",
  92        [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
  93        [PHY_INTERFACE_MODE_XAUI]               = "xaui",
  94        [PHY_INTERFACE_MODE_RXAUI]              = "rxaui",
  95        [PHY_INTERFACE_MODE_SFI]                = "sfi",
  96        [PHY_INTERFACE_MODE_NONE]               = "",
  97};
  98
  99static inline const char *phy_string_for_interface(phy_interface_t i)
 100{
 101        /* Default to unknown */
 102        if (i > PHY_INTERFACE_MODE_NONE)
 103                i = PHY_INTERFACE_MODE_NONE;
 104
 105        return phy_interface_strings[i];
 106}
 107
 108
 109struct phy_device;
 110
 111#define MDIO_NAME_LEN 32
 112
 113struct mii_dev {
 114        struct list_head link;
 115        char name[MDIO_NAME_LEN];
 116        void *priv;
 117        int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
 118        int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
 119                        u16 val);
 120        int (*reset)(struct mii_dev *bus);
 121        struct phy_device *phymap[PHY_MAX_ADDR];
 122        u32 phy_mask;
 123};
 124
 125/* struct phy_driver: a structure which defines PHY behavior
 126 *
 127 * uid will contain a number which represents the PHY.  During
 128 * startup, the driver will poll the PHY to find out what its
 129 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 130 * gotten from the PHY will be masked to
 131 * discard any bits which may change based on revision numbers
 132 * unimportant to functionality
 133 *
 134 */
 135struct phy_driver {
 136        char *name;
 137        unsigned int uid;
 138        unsigned int mask;
 139        unsigned int mmds;
 140
 141        u32 features;
 142
 143        /* Called to do any driver startup necessities */
 144        /* Will be called during phy_connect */
 145        int (*probe)(struct phy_device *phydev);
 146
 147        /* Called to configure the PHY, and modify the controller
 148         * based on the results.  Should be called after phy_connect */
 149        int (*config)(struct phy_device *phydev);
 150
 151        /* Called when starting up the controller */
 152        int (*startup)(struct phy_device *phydev);
 153
 154        /* Called when bringing down the controller */
 155        int (*shutdown)(struct phy_device *phydev);
 156
 157        int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
 158        int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
 159                        u16 val);
 160        struct list_head list;
 161};
 162
 163struct phy_device {
 164        /* Information about the PHY type */
 165        /* And management functions */
 166        struct mii_dev *bus;
 167        struct phy_driver *drv;
 168        void *priv;
 169
 170#ifdef CONFIG_DM_ETH
 171        struct udevice *dev;
 172#else
 173        struct eth_device *dev;
 174#endif
 175
 176        /* forced speed & duplex (no autoneg)
 177         * partner speed & duplex & pause (autoneg)
 178         */
 179        int speed;
 180        int duplex;
 181
 182        /* The most recently read link state */
 183        int link;
 184        int port;
 185        phy_interface_t interface;
 186
 187        u32 advertising;
 188        u32 supported;
 189        u32 mmds;
 190
 191        int autoneg;
 192        int addr;
 193        int pause;
 194        int asym_pause;
 195        u32 phy_id;
 196        u32 flags;
 197};
 198
 199struct fixed_link {
 200        int phy_id;
 201        int duplex;
 202        int link_speed;
 203        int pause;
 204        int asym_pause;
 205};
 206
 207static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 208{
 209        struct mii_dev *bus = phydev->bus;
 210
 211        return bus->read(bus, phydev->addr, devad, regnum);
 212}
 213
 214static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
 215                        u16 val)
 216{
 217        struct mii_dev *bus = phydev->bus;
 218
 219        return bus->write(bus, phydev->addr, devad, regnum, val);
 220}
 221
 222#ifdef CONFIG_PHYLIB_10G
 223extern struct phy_driver gen10g_driver;
 224
 225/* For now, XGMII is the only 10G interface */
 226static inline int is_10g_interface(phy_interface_t interface)
 227{
 228        return interface == PHY_INTERFACE_MODE_XGMII;
 229}
 230
 231#endif
 232
 233int phy_init(void);
 234int phy_reset(struct phy_device *phydev);
 235struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
 236                phy_interface_t interface);
 237#ifdef CONFIG_DM_ETH
 238void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
 239struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 240                                struct udevice *dev,
 241                                phy_interface_t interface);
 242#else
 243void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 244struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 245                                struct eth_device *dev,
 246                                phy_interface_t interface);
 247#endif
 248int phy_startup(struct phy_device *phydev);
 249int phy_config(struct phy_device *phydev);
 250int phy_shutdown(struct phy_device *phydev);
 251int phy_register(struct phy_driver *drv);
 252int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 253int genphy_config_aneg(struct phy_device *phydev);
 254int genphy_restart_aneg(struct phy_device *phydev);
 255int genphy_update_link(struct phy_device *phydev);
 256int genphy_parse_link(struct phy_device *phydev);
 257int genphy_config(struct phy_device *phydev);
 258int genphy_startup(struct phy_device *phydev);
 259int genphy_shutdown(struct phy_device *phydev);
 260int gen10g_config(struct phy_device *phydev);
 261int gen10g_startup(struct phy_device *phydev);
 262int gen10g_shutdown(struct phy_device *phydev);
 263int gen10g_discover_mmds(struct phy_device *phydev);
 264
 265int phy_mv88e61xx_init(void);
 266int phy_aquantia_init(void);
 267int phy_atheros_init(void);
 268int phy_broadcom_init(void);
 269int phy_cortina_init(void);
 270int phy_davicom_init(void);
 271int phy_et1011c_init(void);
 272int phy_lxt_init(void);
 273int phy_marvell_init(void);
 274int phy_micrel_ksz8xxx_init(void);
 275int phy_micrel_ksz90x1_init(void);
 276int phy_meson_gxl_init(void);
 277int phy_natsemi_init(void);
 278int phy_realtek_init(void);
 279int phy_smsc_init(void);
 280int phy_teranetics_init(void);
 281int phy_ti_init(void);
 282int phy_vitesse_init(void);
 283int phy_xilinx_init(void);
 284int phy_mscc_init(void);
 285int phy_fixed_init(void);
 286int phy_xilinx_gmii2rgmii_init(void);
 287
 288int board_phy_config(struct phy_device *phydev);
 289int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
 290
 291/**
 292 * phy_get_interface_by_name() - Look up a PHY interface name
 293 *
 294 * @str:        PHY interface name, e.g. "mii"
 295 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 296 */
 297int phy_get_interface_by_name(const char *str);
 298
 299/**
 300 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 301 * is RGMII (all variants)
 302 * @phydev: the phy_device struct
 303 */
 304static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 305{
 306        return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
 307                phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 308}
 309
 310/**
 311 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 312 * is SGMII (all variants)
 313 * @phydev: the phy_device struct
 314 */
 315static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 316{
 317        return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
 318                phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
 319}
 320
 321/* PHY UIDs for various PHYs that are referenced in external code */
 322#define PHY_UID_CS4340  0x13e51002
 323#define PHY_UID_TN2020  0x00a19410
 324
 325#endif
 326