LXR uboot/arch/arm/cpu/armv8/fsl-layerscape/lx2160a

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2018 NXP
   4 */
   5
   6#include <common.h>
   7#include <asm/arch/fsl_serdes.h>
   8
   9struct serdes_config {
  10        u8 protocol;
  11        u8 lanes[SRDS_MAX_LANES];
  12};
  13
  14static struct serdes_config serdes1_cfg_tbl[] = {
  15        /* SerDes 1 */
  16        {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
  17        {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } },
  18        {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4,
  19                XFI3 } },
  20        {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4,
  21                SGMII3 } },
  22        {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1,
  23                PCIE1 } },
  24        {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4,
  25                XFI3 } },
  26        {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4,
  27                XFI3 } },
  28        {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } },
  29        {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4,
  30                PCIE1 } },
  31        {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } },
  32        {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } },
  33        {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
  34        {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1,
  35                _100GE1 } },
  36        {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1,
  37                _100GE1 } },
  38        {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } },
  39        {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } },
  40        {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } },
  41        {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4,
  42                XFI3 } },
  43        {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } },
  44        {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1,
  45                _40GE1 } },
  46        {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4,
  47                _25GE3 } },
  48        {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
  49        {}
  50};
  51
  52static struct serdes_config serdes2_cfg_tbl[] = {
  53        /* SerDes 2 */
  54        {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } },
  55        {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
  56        {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  57        {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
  58        {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } },
  59        {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13,
  60                XFI14 } },
  61        {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13,
  62                XFI14 } },
  63        {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } },
  64        {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13,
  65                SGMII14} },
  66        {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4,
  67                PCIE4 } },
  68        {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13,
  69                SGMII14 } },
  70        {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1,
  71                SATA2 } },
  72        {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } },
  73        {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13,
  74                SGMII14 } },
  75        {}
  76};
  77
  78static struct serdes_config serdes3_cfg_tbl[] = {
  79        /* SerDes 3 */
  80        {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } },
  81        {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } },
  82        {}
  83};
  84
  85static struct serdes_config *serdes_cfg_tbl[] = {
  86        serdes1_cfg_tbl,
  87        serdes2_cfg_tbl,
  88        serdes3_cfg_tbl,
  89};
  90
  91enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  92{
  93        struct serdes_config *ptr;
  94
  95        if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  96                return 0;
  97
  98        ptr = serdes_cfg_tbl[serdes];
  99        while (ptr->protocol) {
 100                if (ptr->protocol == cfg)
 101                        return ptr->lanes[lane];
 102                ptr++;
 103        }
 104
 105        return 0;
 106}
 107
 108int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 109{
 110        int i;
 111        struct serdes_config *ptr;
 112
 113        if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 114                return 0;
 115
 116        ptr = serdes_cfg_tbl[serdes];
 117        while (ptr->protocol) {
 118                if (ptr->protocol == prtcl)
 119                        break;
 120                ptr++;
 121        }
 122
 123        if (!ptr->protocol)
 124                return 0;
 125
 126        for (i = 0; i < SRDS_MAX_LANES; i++) {
 127                if (ptr->lanes[i] != NONE)
 128                        return 1;
 129        }
 130
 131        return 0;
 132}
 133