LXR uboot/arch/powerpc/cpu/mpc8xx/cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2017
   4 * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
   5 */
   6
   7#include <common.h>
   8#include <asm/processor.h>
   9#include <asm/ppc.h>
  10#include <asm/io.h>
  11#include <asm/mmu.h>
  12
  13int icache_status(void)
  14{
  15        return !!(mfspr(IC_CST) & IDC_ENABLED);
  16}
  17
  18void icache_enable(void)
  19{
  20        sync();
  21        mtspr(IC_CST, IDC_INVALL);
  22        mtspr(IC_CST, IDC_ENABLE);
  23}
  24
  25void icache_disable(void)
  26{
  27        sync();
  28        mtspr(IC_CST, IDC_DISABLE);
  29}
  30
  31int dcache_status(void)
  32{
  33        return !!(mfspr(IC_CST) & IDC_ENABLED);
  34}
  35
  36void dcache_enable(void)
  37{
  38        mtspr(MD_CTR, MD_RESETVAL);     /* Set cache mode with MMU off */
  39        mtspr(DC_CST, IDC_INVALL);
  40        mtspr(DC_CST, IDC_ENABLE);
  41}
  42
  43void dcache_disable(void)
  44{
  45        sync();
  46        mtspr(DC_CST, IDC_DISABLE);
  47        mtspr(DC_CST, IDC_INVALL);
  48}
  49