LXR uboot/board/compulab/cl-som-imx7/cl-som-imx7.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * U-Boot board functions for CompuLab CL-SOM-iMX7 module
   4 *
   5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
   6 *
   7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
   8 */
   9
  10#include <common.h>
  11#include <environment.h>
  12#include <mmc.h>
  13#include <phy.h>
  14#include <netdev.h>
  15#include <fsl_esdhc.h>
  16#include <power/pmic.h>
  17#include <power/pfuze3000_pmic.h>
  18#include <asm/mach-imx/mxc_i2c.h>
  19#include <asm/mach-imx/iomux-v3.h>
  20#include <asm/arch-mx7/mx7-pins.h>
  21#include <asm/arch-mx7/sys_proto.h>
  22#include <asm/arch-mx7/clock.h>
  23#include "../common/eeprom.h"
  24#include "common.h"
  25
  26DECLARE_GLOBAL_DATA_PTR;
  27
  28#ifdef CONFIG_SYS_I2C_MXC
  29
  30#define I2C_PAD_CTRL            (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  31                                PAD_CTL_HYS)
  32
  33#define CL_SOM_IMX7_GPIO_I2C2_SCL       IMX_GPIO_NR(1, 6)
  34#define CL_SOM_IMX7_GPIO_I2C2_SDA       IMX_GPIO_NR(1, 7)
  35
  36static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
  37        .scl = {
  38                .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
  39                        MUX_PAD_CTRL(I2C_PAD_CTRL),
  40                .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
  41                        MUX_PAD_CTRL(I2C_PAD_CTRL),
  42                .gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
  43        },
  44        .sda = {
  45                .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
  46                        MUX_PAD_CTRL(I2C_PAD_CTRL),
  47                .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
  48                        MUX_PAD_CTRL(I2C_PAD_CTRL),
  49                .gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
  50        },
  51};
  52
  53/*
  54 * cl_som_imx7_setup_i2c() - I2C  pinmux configuration.
  55 */
  56static void cl_som_imx7_setup_i2c(void)
  57{
  58        setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
  59}
  60#else /* !CONFIG_SYS_I2C_MXC */
  61static void cl_som_imx7_setup_i2c(void) {}
  62#endif /* CONFIG_SYS_I2C_MXC */
  63
  64int dram_init(void)
  65{
  66        gd->ram_size = imx_ddr_size();
  67
  68        return 0;
  69}
  70
  71#ifdef CONFIG_FSL_ESDHC
  72
  73#define CL_SOM_IMX7_GPIO_USDHC3_PWR     IMX_GPIO_NR(6, 11)
  74
  75static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
  76        {USDHC1_BASE_ADDR, 0, 4},
  77        {USDHC3_BASE_ADDR},
  78};
  79
  80int board_mmc_init(bd_t *bis)
  81{
  82        int i, ret;
  83        /*
  84         * According to the board_mmc_init() the following map is done:
  85         * (U-boot device node)    (Physical Port)
  86         * mmc0                    USDHC1
  87         * mmc2                    USDHC3 (eMMC)
  88         */
  89        for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  90                switch (i) {
  91                case 0:
  92                        cl_som_imx7_usdhc1_pads_set();
  93                        gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
  94                        cl_som_imx7_usdhc_cfg[0].sdhc_clk =
  95                                mxc_get_clock(MXC_ESDHC_CLK);
  96                        break;
  97                case 1:
  98                        cl_som_imx7_usdhc3_emmc_pads_set();
  99                        gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
 100                        gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
 101                        udelay(500);
 102                        gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
 103                        cl_som_imx7_usdhc_cfg[1].sdhc_clk =
 104                                mxc_get_clock(MXC_ESDHC3_CLK);
 105                        break;
 106                default:
 107                        printf("Warning: you configured more USDHC controllers "
 108                                "(%d) than supported by the board\n", i + 1);
 109                        return -EINVAL;
 110                }
 111
 112                ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
 113                if (ret)
 114                        return ret;
 115        }
 116
 117        return 0;
 118}
 119#endif /* CONFIG_FSL_ESDHC */
 120
 121#ifdef CONFIG_FEC_MXC
 122
 123#define CL_SOM_IMX7_ETH1_PHY_NRST       IMX_GPIO_NR(1, 4)
 124
 125/*
 126 * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
 127 */
 128static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
 129{
 130        unsigned short val;
 131
 132        /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 133         * which cause ethernet link down/up issue, so disable SmartEEE
 134         */
 135        phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 136        phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 137        phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 138        val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 139        val &= ~(0x1 << 8);
 140        phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 141
 142        /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 143        phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 144        phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 145        phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 146
 147        val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 148        val &= 0xffe3;
 149        val |= 0x18;
 150        phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 151
 152        /* introduce tx clock delay */
 153        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 154        val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 155        val |= 0x0100;
 156        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 157}
 158
 159int board_phy_config(struct phy_device *phydev)
 160{
 161        cl_som_imx7_rgmii_rework(phydev);
 162
 163        if (phydev->drv->config)
 164                phydev->drv->config(phydev);
 165
 166        return 0;
 167}
 168
 169/*
 170 * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
 171 *
 172 * @env_var: MAC address environment variable
 173 * @eeprom_bus: I2C bus of the environment EEPROM
 174 *
 175 * @return: 0 on success, < 0 on failure
 176 */
 177static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
 178{
 179        int ret;
 180        unsigned char enetaddr[6];
 181
 182        ret = eth_env_get_enetaddr(env_var, enetaddr);
 183        if (ret)
 184                return 0;
 185
 186        ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 187        if (ret)
 188                return ret;
 189
 190        ret = is_valid_ethaddr(enetaddr);
 191        if (!ret)
 192                return -1;
 193
 194        return eth_env_set_enetaddr(env_var, enetaddr);
 195}
 196
 197#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
 198
 199int board_eth_init(bd_t *bis)
 200{
 201        /* set Ethernet MAC address environment */
 202        cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
 203        /* Ethernet interface pinmux configuration  */
 204        cl_som_imx7_phy1_rst_pads_set();
 205        cl_som_imx7_fec1_pads_set();
 206        /* PHY reset */
 207        gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
 208        gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
 209        mdelay(10);
 210        gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
 211        /* MAC initialization */
 212        return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
 213                                       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 214}
 215
 216/*
 217 * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
 218 * - ENET1 reference clock mode select.
 219 * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
 220 */
 221static void cl_som_imx7_setup_fec(void)
 222{
 223        struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 224                = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 225
 226        /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
 227        clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 228                        (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 229                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 230
 231        set_clk_enet(ENET_125MHZ);
 232}
 233#else /* !CONFIG_FEC_MXC */
 234static void cl_som_imx7_setup_fec(void) {}
 235#endif /* CONFIG_FEC_MXC */
 236
 237#ifdef CONFIG_SPI
 238
 239static void cl_som_imx7_spi_init(void)
 240{
 241        cl_som_imx7_espi1_pads_set();
 242}
 243#else /* !CONFIG_SPI */
 244static void cl_som_imx7_spi_init(void) {}
 245#endif /* CONFIG_SPI */
 246
 247int board_early_init_f(void)
 248{
 249        cl_som_imx7_uart1_pads_set();
 250        cl_som_imx7_usb_otg1_pads_set();
 251
 252        return 0;
 253}
 254
 255int board_init(void)
 256{
 257        /* address of boot parameters */
 258        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 259        cl_som_imx7_setup_i2c();
 260        cl_som_imx7_setup_fec();
 261        cl_som_imx7_spi_init();
 262
 263        return 0;
 264}
 265
 266#ifdef CONFIG_POWER
 267#define I2C_PMIC        0
 268int power_init_board(void)
 269{
 270        struct pmic *p;
 271        int ret;
 272        unsigned int reg, rev_id;
 273
 274        ret = power_pfuze3000_init(I2C_PMIC);
 275        if (ret)
 276                return ret;
 277
 278        p = pmic_get("PFUZE3000");
 279        ret = pmic_probe(p);
 280        if (ret)
 281                return ret;
 282
 283        pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 284        pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 285        printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 286
 287        /* disable Low Power Mode during standby mode */
 288        pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
 289
 290        return 0;
 291}
 292#endif /* CONFIG_POWER */
 293
 294/*
 295 * cl_som_imx7_setup_wdog() - watchdog configuration.
 296 * - Output WDOG_B signal to reset external pmic.
 297 * - Suspend the watchdog timer during low-power modes.
 298 */
 299void cl_som_imx7_setup_wdog(void)
 300{
 301        struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 302
 303        cl_som_imx7_wdog_pads_set();
 304        set_wdog_reset(wdog);
 305       /*
 306        * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 307        * since we use PMIC_PWRON to reset the board.
 308        */
 309        clrsetbits_le16(&wdog->wcr, 0, 0x10);
 310}
 311
 312int board_late_init(void)
 313{
 314        env_set("board_name", "CL-SOM-iMX7");
 315        cl_som_imx7_setup_wdog();
 316        return 0;
 317}
 318
 319int checkboard(void)
 320{
 321        char *mode;
 322
 323        if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
 324                mode = "secure";
 325        else
 326                mode = "non-secure";
 327
 328        printf("Board: CL-SOM-iMX7 in %s mode\n", mode);
 329
 330        return 0;
 331}
 332