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50#include <common.h>
51#include <netdev.h>
52#include <asm/fsl_serdes.h>
53#include <fm_eth.h>
54#include <fsl_mdio.h>
55#include <malloc.h>
56#include <fdt_support.h>
57#include <fsl_dtsec.h>
58
59#include "../common/ngpixis.h"
60#include "../common/fman.h"
61
62#ifdef CONFIG_FMAN_ENET
63
64#define BRDCFG1_EMI1_SEL_MASK 0x78
65#define BRDCFG1_EMI1_SEL_SLOT1 0x10
66#define BRDCFG1_EMI1_SEL_SLOT2 0x20
67#define BRDCFG1_EMI1_SEL_SLOT5 0x30
68#define BRDCFG1_EMI1_SEL_SLOT6 0x40
69#define BRDCFG1_EMI1_SEL_SLOT7 0x50
70#define BRDCFG1_EMI1_SEL_RGMII 0x00
71#define BRDCFG1_EMI1_EN 0x08
72#define BRDCFG1_EMI2_SEL_MASK 0x06
73#define BRDCFG1_EMI2_SEL_SLOT1 0x00
74#define BRDCFG1_EMI2_SEL_SLOT2 0x02
75
76#define BRDCFG2_REG_GPIO_SEL 0x20
77
78#define PHY_BASE_ADDR 0x00
79
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84
85
86struct {
87 u8 mask;
88 u8 val;
89} mdio_mux[NUM_FM_PORTS];
90
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94
95
96static u8 lane_to_slot[] = {
97 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
98};
99
100
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103
104
105void hydra_mux_mdio(u8 mask, u8 val)
106{
107 clrsetbits_8(&pixis->brdcfg1, mask, val);
108}
109
110struct hydra_mdio {
111 u8 mask;
112 u8 val;
113 struct mii_dev *realbus;
114};
115
116static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
117 int regnum)
118{
119 struct hydra_mdio *priv = bus->priv;
120
121 hydra_mux_mdio(priv->mask, priv->val);
122
123 return priv->realbus->read(priv->realbus, addr, devad, regnum);
124}
125
126static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
127 int regnum, u16 value)
128{
129 struct hydra_mdio *priv = bus->priv;
130
131 hydra_mux_mdio(priv->mask, priv->val);
132
133 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
134}
135
136static int hydra_mdio_reset(struct mii_dev *bus)
137{
138 struct hydra_mdio *priv = bus->priv;
139
140 return priv->realbus->reset(priv->realbus);
141}
142
143static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
144{
145 struct mii_dev *bus = miiphy_get_dev_by_name(name);
146 struct hydra_mdio *priv = bus->priv;
147
148 priv->mask = mask;
149 priv->val = val;
150}
151
152static int hydra_mdio_init(char *realbusname, char *fakebusname)
153{
154 struct hydra_mdio *hmdio;
155 struct mii_dev *bus = mdio_alloc();
156
157 if (!bus) {
158 printf("Failed to allocate Hydra MDIO bus\n");
159 return -1;
160 }
161
162 hmdio = malloc(sizeof(*hmdio));
163 if (!hmdio) {
164 printf("Failed to allocate Hydra private data\n");
165 free(bus);
166 return -1;
167 }
168
169 bus->read = hydra_mdio_read;
170 bus->write = hydra_mdio_write;
171 bus->reset = hydra_mdio_reset;
172 strcpy(bus->name, fakebusname);
173
174 hmdio->realbus = miiphy_get_dev_by_name(realbusname);
175
176 if (!hmdio->realbus) {
177 printf("No bus with name %s\n", realbusname);
178 free(bus);
179 free(hmdio);
180 return -1;
181 }
182
183 bus->priv = hmdio;
184
185 return mdio_register(bus);
186}
187
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195
196
197static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
198{
199 const char *path = fdt_get_alias(fdt, alias);
200
201 if (!path)
202 path = alias;
203
204 do_fixup_by_path(fdt, path, "reg",
205 &mux, sizeof(mux), 1);
206 do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
207 &mux, sizeof(mux), 1);
208}
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237void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
238 enum fm_port port, int offset)
239{
240 unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
241 char phy[16];
242
243 if (port == FM1_10GEC1) {
244
245 int lane = serdes_get_first_lane(XAUI_FM1);
246 if (lane >= 0) {
247
248 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
249 fdt_set_phy_handle(fdt, compat, addr, phy);
250 }
251 return;
252 }
253
254 if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
255
256
257 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
258 fdt_set_phy_handle(fdt, compat, addr, phy);
259 return;
260 }
261
262
263 if (mux) {
264
265 sprintf(phy, "phy_sgmii_%x",
266 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
267 fdt_set_phy_handle(fdt, compat, addr, phy);
268 }
269}
270
271#define PIXIS_SW2_LANE_23_SEL 0x80
272#define PIXIS_SW2_LANE_45_SEL 0x40
273#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
274#define PIXIS_SW2_LANE_67_SEL_5 0x00
275#define PIXIS_SW2_LANE_67_SEL_6 0x20
276#define PIXIS_SW2_LANE_67_SEL_7 0x10
277#define PIXIS_SW2_LANE_8_SEL 0x08
278#define PIXIS_SW2_LANE_1617_SEL 0x04
279
280
281
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284
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286
287
288static void initialize_lane_to_slot(void)
289{
290 u8 sw2 = in_8(&PIXIS_SW(2));
291
292 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
293 lane_to_slot[3] = lane_to_slot[2];
294
295 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
296 lane_to_slot[5] = lane_to_slot[4];
297
298 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
299 case PIXIS_SW2_LANE_67_SEL_5:
300 lane_to_slot[6] = 5;
301 break;
302 case PIXIS_SW2_LANE_67_SEL_6:
303 lane_to_slot[6] = 6;
304 break;
305 case PIXIS_SW2_LANE_67_SEL_7:
306 lane_to_slot[6] = 7;
307 break;
308 }
309 lane_to_slot[7] = lane_to_slot[6];
310
311 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
312
313 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
314 lane_to_slot[17] = lane_to_slot[16];
315}
316
317#endif
318
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330
331
332void fdt_fixup_board_enet(void *fdt)
333{
334#ifdef CONFIG_FMAN_ENET
335 unsigned int i;
336 int lane;
337
338 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
339 int idx = i - FM1_DTSEC1;
340
341 switch (fm_info_get_enet_if(i)) {
342 case PHY_INTERFACE_MODE_SGMII:
343 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
344 if (lane >= 0) {
345 fdt_status_okay_by_alias(fdt, "emi1_sgmii");
346
347 fdt_set_mdio_mux(fdt, "emi1_sgmii",
348 mdio_mux[i].val);
349 }
350 break;
351 case PHY_INTERFACE_MODE_RGMII:
352 fdt_status_okay_by_alias(fdt, "emi1_rgmii");
353 break;
354 default:
355 break;
356 }
357 }
358
359 lane = serdes_get_first_lane(XAUI_FM1);
360 if (lane >= 0)
361 fdt_status_okay_by_alias(fdt, "emi2_xgmii");
362#endif
363}
364
365int board_eth_init(bd_t *bis)
366{
367#ifdef CONFIG_FMAN_ENET
368 struct fsl_pq_mdio_info dtsec_mdio_info;
369 struct tgec_mdio_info tgec_mdio_info;
370 unsigned int i, slot;
371 int lane;
372 struct mii_dev *bus;
373
374 printf("Initializing Fman\n");
375
376 initialize_lane_to_slot();
377
378
379 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
380
381 memset(mdio_mux, 0, sizeof(mdio_mux));
382
383 dtsec_mdio_info.regs =
384 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
385 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
386
387
388 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
389
390 tgec_mdio_info.regs =
391 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
392 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
393
394
395 fm_tgec_mdio_init(bis, &tgec_mdio_info);
396
397
398 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
399 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
400
401
402
403
404
405
406 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
407 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
408 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
409 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
410
411 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
412 int idx = i - FM1_DTSEC1;
413
414 switch (fm_info_get_enet_if(i)) {
415 case PHY_INTERFACE_MODE_SGMII:
416 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
417 if (lane < 0)
418 break;
419 slot = lane_to_slot[lane];
420 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
421 switch (slot) {
422 case 1:
423
424 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
425 BRDCFG1_EMI1_EN;
426 break;
427 case 2:
428 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
429 BRDCFG1_EMI1_EN;
430 break;
431 case 5:
432 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
433 BRDCFG1_EMI1_EN;
434 break;
435 case 6:
436 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
437 BRDCFG1_EMI1_EN;
438 break;
439 case 7:
440 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
441 BRDCFG1_EMI1_EN;
442 break;
443 };
444
445 hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
446 mdio_mux[i].mask, mdio_mux[i].val);
447 fm_info_set_mdio(i,
448 miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
449 break;
450 case PHY_INTERFACE_MODE_RGMII:
451
452
453
454
455
456
457
458 fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
459 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
460 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
461 BRDCFG1_EMI1_EN;
462 hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
463 mdio_mux[i].mask, mdio_mux[i].val);
464 fm_info_set_mdio(i,
465 miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
466 break;
467 case PHY_INTERFACE_MODE_NONE:
468 fm_info_set_phy_address(i, 0);
469 break;
470 default:
471 printf("Fman1: DTSEC%u set to unknown interface %i\n",
472 idx + 1, fm_info_get_enet_if(i));
473 fm_info_set_phy_address(i, 0);
474 break;
475 }
476 }
477
478 bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
479 set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
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494 lane = serdes_get_first_lane(XAUI_FM1);
495 if (lane >= 0) {
496 slot = lane_to_slot[lane];
497 if (slot == 1) {
498
499 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
500 BRDCFG1_EMI2_SEL_SLOT1);
501 fm_info_set_phy_address(FM1_10GEC1,
502 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
503 } else {
504
505 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
506 BRDCFG1_EMI2_SEL_SLOT2);
507 fm_info_set_phy_address(FM1_10GEC1,
508 CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
509 }
510 }
511
512 fm_info_set_mdio(FM1_10GEC1,
513 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
514
515 cpu_eth_init(bis);
516#endif
517
518 return pci_eth_init(bis);
519}
520