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16#include <common.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/arch/hardware.h>
19#include <asm/arch/mux.h>
20#include <asm/io.h>
21#include <i2c.h>
22#include "board.h"
23
24static struct module_pin_mux uart0_pin_mux[] = {
25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
27 {-1},
28};
29
30static struct module_pin_mux mmc0_pin_mux[] = {
31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
37 {-1},
38};
39
40static struct module_pin_mux i2c1_pin_mux[] = {
41 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
42 PULLUDEN | SLEWCTRL)},
43 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
44 PULLUDEN | SLEWCTRL)},
45 {-1},
46};
47
48static struct module_pin_mux rmii1_pin_mux[] = {
49 {OFFSET(mii1_crs), MODE(1) | RXACTIVE},
50 {OFFSET(mii1_txen), MODE(1)},
51 {OFFSET(mii1_txd1), MODE(1)},
52 {OFFSET(mii1_txd0), MODE(1)},
53 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},
54 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},
55 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},
56 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
57 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
58 {-1},
59};
60
61static struct module_pin_mux rgmii2_pin_mux[] = {
62 {OFFSET(gpmc_a0), MODE(2)},
63 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE},
64 {OFFSET(gpmc_a2), MODE(2)},
65 {OFFSET(gpmc_a3), MODE(2)},
66 {OFFSET(gpmc_a4), MODE(2)},
67 {OFFSET(gpmc_a5), MODE(2)},
68 {OFFSET(gpmc_a6), MODE(2)},
69 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE},
70 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE},
71 {OFFSET(gpmc_a9), MODE(2) | RXACTIVE},
72 {OFFSET(gpmc_a10), MODE(2) | RXACTIVE},
73 {OFFSET(gpmc_a11), MODE(2) | RXACTIVE},
74 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
75 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
76 {-1},
77};
78
79static struct module_pin_mux nand_pin_mux[] = {
80 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},
81 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},
82 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},
83 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},
84 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},
85 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},
86 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},
87 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},
88 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
89 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},
90 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},
91 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},
92 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},
93 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},
94 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},
95 {-1},
96};
97
98void enable_uart0_pin_mux(void)
99{
100 configure_module_pin_mux(uart0_pin_mux);
101}
102
103void enable_i2c1_pin_mux(void)
104{
105 configure_module_pin_mux(i2c1_pin_mux);
106}
107
108void enable_board_pin_mux()
109{
110 configure_module_pin_mux(i2c1_pin_mux);
111 configure_module_pin_mux(rgmii2_pin_mux);
112 configure_module_pin_mux(rmii1_pin_mux);
113 configure_module_pin_mux(mmc0_pin_mux);
114
115#if defined(CONFIG_NAND)
116 configure_module_pin_mux(nand_pin_mux);
117#endif
118}
119