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5
6#include <common.h>
7#include <malloc.h>
8#include <linux/compiler.h>
9#include <linux/err.h>
10#include <asm/io.h>
11
12#define TX_NUM_DESC 1
13#define RX_NUM_DESC 32
14
15#define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
16
17#define ETH_BUF_SZ 2048
18#define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
19#define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
20
21#define RXSTART 0x00000002
22#define TXSTART 0x00002000
23
24#define RXENABLE 0x00000004
25#define TXENABLE 0x00000008
26
27#define XGMAC_CONTROL_SPD 0x40000000
28#define XGMAC_CONTROL_SPD_MASK 0x60000000
29#define XGMAC_CONTROL_SARC 0x10000000
30#define XGMAC_CONTROL_SARK_MASK 0x18000000
31#define XGMAC_CONTROL_CAR 0x04000000
32#define XGMAC_CONTROL_CAR_MASK 0x06000000
33#define XGMAC_CONTROL_CAR_SHIFT 25
34#define XGMAC_CONTROL_DP 0x01000000
35#define XGMAC_CONTROL_WD 0x00800000
36#define XGMAC_CONTROL_JD 0x00400000
37#define XGMAC_CONTROL_JE 0x00100000
38#define XGMAC_CONTROL_LM 0x00001000
39#define XGMAC_CONTROL_IPC 0x00000400
40#define XGMAC_CONTROL_ACS 0x00000080
41#define XGMAC_CONTROL_DDIC 0x00000010
42#define XGMAC_CONTROL_TE 0x00000008
43#define XGMAC_CONTROL_RE 0x00000004
44
45#define XGMAC_DMA_BUSMODE_RESET 0x00000001
46#define XGMAC_DMA_BUSMODE_DSL 0x00000004
47#define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
48#define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
49#define XGMAC_DMA_BUSMODE_ATDS 0x00000080
50#define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
51#define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
52#define XGMAC_DMA_BUSMODE_FB 0x00010000
53#define XGMAC_DMA_BUSMODE_USP 0x00800000
54#define XGMAC_DMA_BUSMODE_8PBL 0x01000000
55#define XGMAC_DMA_BUSMODE_AAL 0x02000000
56
57#define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
58#define XGMAC_DMA_AXIMODE_MGK 0x40000000
59#define XGMAC_DMA_AXIMODE_WROSR 0x00100000
60#define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
61#define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
62#define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
63#define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
64#define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
65#define XGMAC_DMA_AXIMODE_AAL 0x00001000
66#define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
67#define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
68#define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
69#define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
70#define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
71#define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
72#define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
73#define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
74
75#define XGMAC_CORE_OMR_RTC_SHIFT 3
76#define XGMAC_CORE_OMR_RTC_MASK 0x00000018
77#define XGMAC_CORE_OMR_RTC 0x00000010
78#define XGMAC_CORE_OMR_RSF 0x00000020
79#define XGMAC_CORE_OMR_DT 0x00000040
80#define XGMAC_CORE_OMR_FEF 0x00000080
81#define XGMAC_CORE_OMR_EFC 0x00000100
82#define XGMAC_CORE_OMR_RFA_SHIFT 9
83#define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
84#define XGMAC_CORE_OMR_RFD_SHIFT 12
85#define XGMAC_CORE_OMR_RFD_MASK 0x00007000
86#define XGMAC_CORE_OMR_TTC_SHIFT 16
87#define XGMAC_CORE_OMR_TTC_MASK 0x00030000
88#define XGMAC_CORE_OMR_TTC 0x00020000
89#define XGMAC_CORE_OMR_FTF 0x00100000
90#define XGMAC_CORE_OMR_TSF 0x00200000
91
92#define FIFO_MINUS_1K 0x0
93#define FIFO_MINUS_2K 0x1
94#define FIFO_MINUS_3K 0x2
95#define FIFO_MINUS_4K 0x3
96#define FIFO_MINUS_6K 0x4
97#define FIFO_MINUS_8K 0x5
98#define FIFO_MINUS_12K 0x6
99#define FIFO_MINUS_16K 0x7
100
101#define XGMAC_CORE_FLOW_PT_SHIFT 16
102#define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
103#define XGMAC_CORE_FLOW_PT 0x00010000
104#define XGMAC_CORE_FLOW_DZQP 0x00000080
105#define XGMAC_CORE_FLOW_PLT_SHIFT 4
106#define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
107#define XGMAC_CORE_FLOW_PLT 0x00000010
108#define XGMAC_CORE_FLOW_UP 0x00000008
109#define XGMAC_CORE_FLOW_RFE 0x00000004
110#define XGMAC_CORE_FLOW_TFE 0x00000002
111#define XGMAC_CORE_FLOW_FCB 0x00000001
112
113
114#define MAX_DESC_BUF_SZ (0x2000 - 8)
115
116#define RXDESC_EXT_STATUS 0x00000001
117#define RXDESC_CRC_ERR 0x00000002
118#define RXDESC_RX_ERR 0x00000008
119#define RXDESC_RX_WDOG 0x00000010
120#define RXDESC_FRAME_TYPE 0x00000020
121#define RXDESC_GIANT_FRAME 0x00000080
122#define RXDESC_LAST_SEG 0x00000100
123#define RXDESC_FIRST_SEG 0x00000200
124#define RXDESC_VLAN_FRAME 0x00000400
125#define RXDESC_OVERFLOW_ERR 0x00000800
126#define RXDESC_LENGTH_ERR 0x00001000
127#define RXDESC_SA_FILTER_FAIL 0x00002000
128#define RXDESC_DESCRIPTOR_ERR 0x00004000
129#define RXDESC_ERROR_SUMMARY 0x00008000
130#define RXDESC_FRAME_LEN_OFFSET 16
131#define RXDESC_FRAME_LEN_MASK 0x3fff0000
132#define RXDESC_DA_FILTER_FAIL 0x40000000
133
134#define RXDESC1_END_RING 0x00008000
135
136#define RXDESC_IP_PAYLOAD_MASK 0x00000003
137#define RXDESC_IP_PAYLOAD_UDP 0x00000001
138#define RXDESC_IP_PAYLOAD_TCP 0x00000002
139#define RXDESC_IP_PAYLOAD_ICMP 0x00000003
140#define RXDESC_IP_HEADER_ERR 0x00000008
141#define RXDESC_IP_PAYLOAD_ERR 0x00000010
142#define RXDESC_IPV4_PACKET 0x00000040
143#define RXDESC_IPV6_PACKET 0x00000080
144#define TXDESC_UNDERFLOW_ERR 0x00000001
145#define TXDESC_JABBER_TIMEOUT 0x00000002
146#define TXDESC_LOCAL_FAULT 0x00000004
147#define TXDESC_REMOTE_FAULT 0x00000008
148#define TXDESC_VLAN_FRAME 0x00000010
149#define TXDESC_FRAME_FLUSHED 0x00000020
150#define TXDESC_IP_HEADER_ERR 0x00000040
151#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
152#define TXDESC_ERROR_SUMMARY 0x00008000
153#define TXDESC_SA_CTRL_INSERT 0x00040000
154#define TXDESC_SA_CTRL_REPLACE 0x00080000
155#define TXDESC_2ND_ADDR_CHAINED 0x00100000
156#define TXDESC_END_RING 0x00200000
157#define TXDESC_CSUM_IP 0x00400000
158#define TXDESC_CSUM_IP_PAYLD 0x00800000
159#define TXDESC_CSUM_ALL 0x00C00000
160#define TXDESC_CRC_EN_REPLACE 0x01000000
161#define TXDESC_CRC_EN_APPEND 0x02000000
162#define TXDESC_DISABLE_PAD 0x04000000
163#define TXDESC_FIRST_SEG 0x10000000
164#define TXDESC_LAST_SEG 0x20000000
165#define TXDESC_INTERRUPT 0x40000000
166
167#define DESC_OWN 0x80000000
168#define DESC_BUFFER1_SZ_MASK 0x00001fff
169#define DESC_BUFFER2_SZ_MASK 0x1fff0000
170#define DESC_BUFFER2_SZ_OFFSET 16
171
172struct xgmac_regs {
173 u32 config;
174 u32 framefilter;
175 u32 resv_1[4];
176 u32 flow_control;
177 u32 vlantag;
178 u32 version;
179 u32 vlaninclude;
180 u32 resv_2[2];
181 u32 pacestretch;
182 u32 vlanhash;
183 u32 resv_3;
184 u32 intreg;
185 struct {
186 u32 hi;
187 u32 lo;
188 } macaddr[16];
189 u32 resv_4[0xd0];
190 u32 core_opmode;
191 u32 resv_5[0x2bf];
192 u32 busmode;
193 u32 txpoll;
194 u32 rxpoll;
195 u32 rxdesclist;
196 u32 txdesclist;
197 u32 dma_status;
198 u32 dma_opmode;
199 u32 intenable;
200 u32 resv_6[2];
201 u32 axi_mode;
202};
203
204struct xgmac_dma_desc {
205 __le32 flags;
206 __le32 buf_size;
207 __le32 buf1_addr;
208 __le32 buf2_addr;
209 __le32 ext_status;
210 __le32 res[3];
211};
212
213
214static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
215{
216 if (buf_sz > MAX_DESC_BUF_SZ)
217 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
218 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
219 else
220 p->buf_size = cpu_to_le32(buf_sz);
221}
222
223static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
224{
225 u32 len = le32_to_cpu(p->buf_size);
226 return (len & DESC_BUFFER1_SZ_MASK) +
227 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
228}
229
230static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
231 int buf_sz)
232{
233 struct xgmac_dma_desc *end = p + ring_size - 1;
234
235 memset(p, 0, sizeof(*p) * ring_size);
236
237 for (; p <= end; p++)
238 desc_set_buf_len(p, buf_sz);
239
240 end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
241}
242
243static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
244{
245 memset(p, 0, sizeof(*p) * ring_size);
246 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
247}
248
249static inline int desc_get_owner(struct xgmac_dma_desc *p)
250{
251 return le32_to_cpu(p->flags) & DESC_OWN;
252}
253
254static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
255{
256
257 p->flags = cpu_to_le32(DESC_OWN);
258}
259
260static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
261{
262 u32 tmpflags = le32_to_cpu(p->flags);
263 tmpflags &= TXDESC_END_RING;
264 tmpflags |= flags | DESC_OWN;
265 p->flags = cpu_to_le32(tmpflags);
266}
267
268static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
269{
270 return (void *)le32_to_cpu(p->buf1_addr);
271}
272
273static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
274 void *paddr, int len)
275{
276 p->buf1_addr = cpu_to_le32(paddr);
277 if (len > MAX_DESC_BUF_SZ)
278 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
279}
280
281static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
282 void *paddr, int len)
283{
284 desc_set_buf_len(p, len);
285 desc_set_buf_addr(p, paddr, len);
286}
287
288static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
289{
290 u32 data = le32_to_cpu(p->flags);
291 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
292 if (data & RXDESC_FRAME_TYPE)
293 len -= 4;
294
295 return len;
296}
297
298struct calxeda_eth_dev {
299 struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
300 struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
301 char rxbuffer[RX_BUF_SZ];
302
303 u32 tx_currdesc;
304 u32 rx_currdesc;
305
306 struct eth_device *dev;
307} __aligned(32);
308
309
310
311
312
313
314static void init_rx_desc(struct calxeda_eth_dev *priv)
315{
316 struct xgmac_dma_desc *rxdesc = priv->rx_chain;
317 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
318 void *rxbuffer = priv->rxbuffer;
319 int i;
320
321 desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
322 writel((ulong)rxdesc, ®s->rxdesclist);
323
324 for (i = 0; i < RX_NUM_DESC; i++) {
325 desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
326 ETH_BUF_SZ);
327 desc_set_rx_owner(rxdesc + i);
328 }
329}
330
331static void init_tx_desc(struct calxeda_eth_dev *priv)
332{
333 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
334
335 desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
336 writel((ulong)priv->tx_chain, ®s->txdesclist);
337}
338
339static int xgmac_reset(struct eth_device *dev)
340{
341 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
342 int timeout = MAC_TIMEOUT;
343 u32 value;
344
345 value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK;
346
347 writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode);
348 while ((timeout-- >= 0) &&
349 (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET))
350 udelay(1);
351
352 writel(value, ®s->config);
353
354 return timeout;
355}
356
357static void xgmac_hwmacaddr(struct eth_device *dev)
358{
359 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
360 u32 macaddr[2];
361
362 memcpy(macaddr, dev->enetaddr, 6);
363 writel(macaddr[1], ®s->macaddr[0].hi);
364 writel(macaddr[0], ®s->macaddr[0].lo);
365}
366
367static int xgmac_init(struct eth_device *dev, bd_t * bis)
368{
369 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
370 struct calxeda_eth_dev *priv = dev->priv;
371 int value;
372
373 if (xgmac_reset(dev) < 0)
374 return -1;
375
376
377 xgmac_hwmacaddr(dev);
378
379
380 value = XGMAC_DMA_BUSMODE_ATDS |
381 (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
382 XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
383 writel(value, ®s->busmode);
384
385 value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
386 XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
387 writel(value, ®s->axi_mode);
388
389
390 value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
391 (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
392 XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
393 writel(value, ®s->core_opmode);
394
395
396 value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
397 (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
398 XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
399 writel(value, ®s->flow_control);
400
401
402 init_rx_desc(priv);
403 init_tx_desc(priv);
404
405
406 priv->tx_currdesc = 0;
407 priv->rx_currdesc = 0;
408
409
410 value = readl(®s->config);
411 value &= XGMAC_CONTROL_SPD_MASK;
412 value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
413 XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
414
415
416 value |= RXENABLE | TXENABLE;
417 writel(value, ®s->config);
418
419 value = readl(®s->dma_opmode);
420 value |= RXSTART | TXSTART;
421 writel(value, ®s->dma_opmode);
422
423 return 0;
424}
425
426static int xgmac_tx(struct eth_device *dev, void *packet, int length)
427{
428 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
429 struct calxeda_eth_dev *priv = dev->priv;
430 u32 currdesc = priv->tx_currdesc;
431 struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
432 int timeout;
433
434 desc_set_buf_addr_and_size(txdesc, packet, length);
435 desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
436 TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
437
438
439 writel(1, ®s->txpoll);
440
441 timeout = 1000000;
442 while (desc_get_owner(txdesc)) {
443 if (timeout-- < 0) {
444 printf("xgmac: TX timeout\n");
445 return -ETIMEDOUT;
446 }
447 udelay(1);
448 }
449
450 priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
451 return 0;
452}
453
454static int xgmac_rx(struct eth_device *dev)
455{
456 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
457 struct calxeda_eth_dev *priv = dev->priv;
458 u32 currdesc = priv->rx_currdesc;
459 struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
460 int length = 0;
461
462
463 if (desc_get_owner(rxdesc))
464 return -1;
465
466 length = desc_get_rx_frame_len(rxdesc);
467
468 net_process_received_packet(desc_get_buf_addr(rxdesc), length);
469
470
471 desc_set_rx_owner(rxdesc);
472 writel(1, ®s->rxpoll);
473
474 priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
475
476 return length;
477}
478
479static void xgmac_halt(struct eth_device *dev)
480{
481 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
482 struct calxeda_eth_dev *priv = dev->priv;
483 int value;
484
485
486 value = readl(®s->config);
487 value &= ~(RXENABLE | TXENABLE);
488 writel(value, ®s->config);
489
490
491 value = readl(®s->dma_opmode);
492 value &= ~(RXSTART | TXSTART);
493 writel(value, ®s->dma_opmode);
494
495
496 priv->tx_currdesc = 0;
497 priv->rx_currdesc = 0;
498}
499
500int calxedaxgmac_initialize(u32 id, ulong base_addr)
501{
502 struct eth_device *dev;
503 struct calxeda_eth_dev *priv;
504 struct xgmac_regs *regs;
505 u32 macaddr[2];
506
507 regs = (struct xgmac_regs *)base_addr;
508
509
510 if (readl(®s->version) != 0x1012)
511 return -1;
512
513 dev = malloc(sizeof(*dev));
514 if (!dev)
515 return 0;
516 memset(dev, 0, sizeof(*dev));
517
518
519 priv = memalign(32, sizeof(*priv));
520 if (!priv) {
521 free(dev);
522 return 0;
523 }
524
525 dev->iobase = (int)base_addr;
526 dev->priv = priv;
527 priv->dev = dev;
528 sprintf(dev->name, "xgmac%d", id);
529
530
531 macaddr[1] = readl(®s->macaddr[0].hi);
532 macaddr[0] = readl(®s->macaddr[0].lo);
533 memcpy(dev->enetaddr, macaddr, 6);
534
535 dev->init = xgmac_init;
536 dev->send = xgmac_tx;
537 dev->recv = xgmac_rx;
538 dev->halt = xgmac_halt;
539
540 eth_register(dev);
541
542 return 1;
543}
544
