LXR uboot/drivers/net/dc2114x.c

   1// SPDX-License-Identifier: GPL-2.0+
   2
   3#include <common.h>
   4#include <malloc.h>
   5#include <net.h>
   6#include <netdev.h>
   7#include <pci.h>
   8
   9#undef DEBUG_SROM
  10#undef DEBUG_SROM2
  11
  12#undef UPDATE_SROM
  13
  14/* PCI Registers.
  15 */
  16#define PCI_CFDA_PSM            0x43
  17
  18#define CFRV_RN         0x000000f0      /* Revision Number */
  19
  20#define WAKEUP          0x00            /* Power Saving Wakeup */
  21#define SLEEP           0x80            /* Power Saving Sleep Mode */
  22
  23#define DC2114x_BRK     0x0020          /* CFRV break between DC21142 & DC21143 */
  24
  25/* Ethernet chip registers.
  26 */
  27#define DE4X5_BMR       0x000           /* Bus Mode Register */
  28#define DE4X5_TPD       0x008           /* Transmit Poll Demand Reg */
  29#define DE4X5_RRBA      0x018           /* RX Ring Base Address Reg */
  30#define DE4X5_TRBA      0x020           /* TX Ring Base Address Reg */
  31#define DE4X5_STS       0x028           /* Status Register */
  32#define DE4X5_OMR       0x030           /* Operation Mode Register */
  33#define DE4X5_SICR      0x068           /* SIA Connectivity Register */
  34#define DE4X5_APROM     0x048           /* Ethernet Address PROM */
  35
  36/* Register bits.
  37 */
  38#define BMR_SWR         0x00000001      /* Software Reset */
  39#define STS_TS          0x00700000      /* Transmit Process State */
  40#define STS_RS          0x000e0000      /* Receive Process State */
  41#define OMR_ST          0x00002000      /* Start/Stop Transmission Command */
  42#define OMR_SR          0x00000002      /* Start/Stop Receive */
  43#define OMR_PS          0x00040000      /* Port Select */
  44#define OMR_SDP         0x02000000      /* SD Polarity - MUST BE ASSERTED */
  45#define OMR_PM          0x00000080      /* Pass All Multicast */
  46
  47/* Descriptor bits.
  48 */
  49#define R_OWN           0x80000000      /* Own Bit */
  50#define RD_RER          0x02000000      /* Receive End Of Ring */
  51#define RD_LS           0x00000100      /* Last Descriptor */
  52#define RD_ES           0x00008000      /* Error Summary */
  53#define TD_TER          0x02000000      /* Transmit End Of Ring */
  54#define T_OWN           0x80000000      /* Own Bit */
  55#define TD_LS           0x40000000      /* Last Segment */
  56#define TD_FS           0x20000000      /* First Segment */
  57#define TD_ES           0x00008000      /* Error Summary */
  58#define TD_SET          0x08000000      /* Setup Packet */
  59
  60/* The EEPROM commands include the alway-set leading bit. */
  61#define SROM_WRITE_CMD  5
  62#define SROM_READ_CMD   6
  63#define SROM_ERASE_CMD  7
  64
  65#define SROM_HWADD          0x0014      /* Hardware Address offset in SROM */
  66#define SROM_RD         0x00004000      /* Read from Boot ROM */
  67#define EE_DATA_WRITE         0x04      /* EEPROM chip data in. */
  68#define EE_WRITE_0          0x4801
  69#define EE_WRITE_1          0x4805
  70#define EE_DATA_READ          0x08      /* EEPROM chip data out. */
  71#define SROM_SR         0x00000800      /* Select Serial ROM when set */
  72
  73#define DT_IN           0x00000004      /* Serial Data In */
  74#define DT_CLK          0x00000002      /* Serial ROM Clock */
  75#define DT_CS           0x00000001      /* Serial ROM Chip Select */
  76
  77#define POLL_DEMAND     1
  78
  79#ifdef CONFIG_TULIP_FIX_DAVICOM
  80#define RESET_DM9102(dev) {\
  81    unsigned long i;\
  82    i=INL(dev, 0x0);\
  83    udelay(1000);\
  84    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
  85    udelay(1000);\
  86}
  87#else
  88#define RESET_DE4X5(dev) {\
  89    int i;\
  90    i=INL(dev, DE4X5_BMR);\
  91    udelay(1000);\
  92    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
  93    udelay(1000);\
  94    OUTL(dev, i, DE4X5_BMR);\
  95    udelay(1000);\
  96    for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
  97    udelay(1000);\
  98}
  99#endif
 100
 101#define START_DE4X5(dev) {\
 102    s32 omr; \
 103    omr = INL(dev, DE4X5_OMR);\
 104    omr |= OMR_ST | OMR_SR;\
 105    OUTL(dev, omr, DE4X5_OMR);          /* Enable the TX and/or RX */\
 106}
 107
 108#define STOP_DE4X5(dev) {\
 109    s32 omr; \
 110    omr = INL(dev, DE4X5_OMR);\
 111    omr &= ~(OMR_ST|OMR_SR);\
 112    OUTL(dev, omr, DE4X5_OMR);          /* Disable the TX and/or RX */ \
 113}
 114
 115#define NUM_RX_DESC PKTBUFSRX
 116#ifndef CONFIG_TULIP_FIX_DAVICOM
 117        #define NUM_TX_DESC 1                   /* Number of TX descriptors   */
 118#else
 119        #define NUM_TX_DESC 4
 120#endif
 121#define RX_BUFF_SZ  PKTSIZE_ALIGN
 122
 123#define TOUT_LOOP   1000000
 124
 125#define SETUP_FRAME_LEN 192
 126
 127struct de4x5_desc {
 128        volatile s32 status;
 129        u32 des1;
 130        u32 buf;
 131        u32 next;
 132};
 133
 134static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring         */
 135static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring         */
 136static int rx_new;                             /* RX descriptor ring pointer */
 137static int tx_new;                             /* TX descriptor ring pointer */
 138
 139static char rxRingSize;
 140static char txRingSize;
 141
 142#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
 143static void  sendto_srom(struct eth_device* dev, u_int command, u_long addr);
 144static int   getfrom_srom(struct eth_device* dev, u_long addr);
 145static int   do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
 146static int   do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
 147#endif  /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 148#ifdef UPDATE_SROM
 149static int   write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
 150static void  update_srom(struct eth_device *dev, bd_t *bis);
 151#endif
 152#ifndef CONFIG_TULIP_FIX_DAVICOM
 153static int   read_srom(struct eth_device *dev, u_long ioaddr, int index);
 154static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
 155#endif  /* CONFIG_TULIP_FIX_DAVICOM */
 156static void  send_setup_frame(struct eth_device* dev, bd_t * bis);
 157
 158static int   dc21x4x_init(struct eth_device* dev, bd_t* bis);
 159static int   dc21x4x_send(struct eth_device *dev, void *packet, int length);
 160static int   dc21x4x_recv(struct eth_device* dev);
 161static void  dc21x4x_halt(struct eth_device* dev);
 162#ifdef CONFIG_TULIP_SELECT_MEDIA
 163extern void  dc21x4x_select_media(struct eth_device* dev);
 164#endif
 165
 166#if defined(CONFIG_E500)
 167#define phys_to_bus(a) (a)
 168#else
 169#define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)dev->priv, a)
 170#endif
 171
 172static int INL(struct eth_device* dev, u_long addr)
 173{
 174        return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
 175}
 176
 177static void OUTL(struct eth_device* dev, int command, u_long addr)
 178{
 179        *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
 180}
 181
 182static struct pci_device_id supported[] = {
 183        { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
 184        { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
 185#ifdef CONFIG_TULIP_FIX_DAVICOM
 186        { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
 187#endif
 188        { }
 189};
 190
 191int dc21x4x_initialize(bd_t *bis)
 192{
 193        int                     idx=0;
 194        int                     card_number = 0;
 195        unsigned int            cfrv;
 196        unsigned char           timer;
 197        pci_dev_t               devbusfn;
 198        unsigned int            iobase;
 199        unsigned short          status;
 200        struct eth_device*      dev;
 201
 202        while(1) {
 203                devbusfn =  pci_find_devices(supported, idx++);
 204                if (devbusfn == -1) {
 205                        break;
 206                }
 207
 208                /* Get the chip configuration revision register. */
 209                pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
 210
 211#ifndef CONFIG_TULIP_FIX_DAVICOM
 212                if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
 213                        printf("Error: The chip is not DC21143.\n");
 214                        continue;
 215                }
 216#endif
 217
 218                pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 219                status |=
 220#ifdef CONFIG_TULIP_USE_IO
 221                  PCI_COMMAND_IO |
 222#else
 223                  PCI_COMMAND_MEMORY |
 224#endif
 225                  PCI_COMMAND_MASTER;
 226                pci_write_config_word(devbusfn, PCI_COMMAND, status);
 227
 228                pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 229#ifdef CONFIG_TULIP_USE_IO
 230                if (!(status & PCI_COMMAND_IO)) {
 231                        printf("Error: Can not enable I/O access.\n");
 232                        continue;
 233                }
 234#else
 235                if (!(status & PCI_COMMAND_MEMORY)) {
 236                        printf("Error: Can not enable MEMORY access.\n");
 237                        continue;
 238                }
 239#endif
 240
 241                if (!(status & PCI_COMMAND_MASTER)) {
 242                        printf("Error: Can not enable Bus Mastering.\n");
 243                        continue;
 244                }
 245
 246                /* Check the latency timer for values >= 0x60. */
 247                pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
 248
 249                if (timer < 0x60) {
 250                        pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
 251                }
 252
 253#ifdef CONFIG_TULIP_USE_IO
 254                /* read BAR for memory space access */
 255                pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
 256                iobase &= PCI_BASE_ADDRESS_IO_MASK;
 257#else
 258                /* read BAR for memory space access */
 259                pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
 260                iobase &= PCI_BASE_ADDRESS_MEM_MASK;
 261#endif
 262                debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
 263
 264                dev = (struct eth_device*) malloc(sizeof *dev);
 265
 266                if (!dev) {
 267                        printf("Can not allocalte memory of dc21x4x\n");
 268                        break;
 269                }
 270                memset(dev, 0, sizeof(*dev));
 271
 272#ifdef CONFIG_TULIP_FIX_DAVICOM
 273                sprintf(dev->name, "Davicom#%d", card_number);
 274#else
 275                sprintf(dev->name, "dc21x4x#%d", card_number);
 276#endif
 277
 278#ifdef CONFIG_TULIP_USE_IO
 279                dev->iobase = pci_io_to_phys(devbusfn, iobase);
 280#else
 281                dev->iobase = pci_mem_to_phys(devbusfn, iobase);
 282#endif
 283                dev->priv   = (void*) devbusfn;
 284                dev->init   = dc21x4x_init;
 285                dev->halt   = dc21x4x_halt;
 286                dev->send   = dc21x4x_send;
 287                dev->recv   = dc21x4x_recv;
 288
 289                /* Ensure we're not sleeping. */
 290                pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
 291
 292                udelay(10 * 1000);
 293
 294#ifndef CONFIG_TULIP_FIX_DAVICOM
 295                read_hw_addr(dev, bis);
 296#endif
 297                eth_register(dev);
 298
 299                card_number++;
 300        }
 301
 302        return card_number;
 303}
 304
 305static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
 306{
 307        int             i;
 308        int             devbusfn = (int) dev->priv;
 309
 310        /* Ensure we're not sleeping. */
 311        pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
 312
 313#ifdef CONFIG_TULIP_FIX_DAVICOM
 314        RESET_DM9102(dev);
 315#else
 316        RESET_DE4X5(dev);
 317#endif
 318
 319        if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
 320                printf("Error: Cannot reset ethernet controller.\n");
 321                return -1;
 322        }
 323
 324#ifdef CONFIG_TULIP_SELECT_MEDIA
 325        dc21x4x_select_media(dev);
 326#else
 327        OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
 328#endif
 329
 330        for (i = 0; i < NUM_RX_DESC; i++) {
 331                rx_ring[i].status = cpu_to_le32(R_OWN);
 332                rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
 333                rx_ring[i].buf = cpu_to_le32(
 334                        phys_to_bus((u32)net_rx_packets[i]));
 335#ifdef CONFIG_TULIP_FIX_DAVICOM
 336                rx_ring[i].next = cpu_to_le32(
 337                        phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC]));
 338#else
 339                rx_ring[i].next = 0;
 340#endif
 341        }
 342
 343        for (i=0; i < NUM_TX_DESC; i++) {
 344                tx_ring[i].status = 0;
 345                tx_ring[i].des1 = 0;
 346                tx_ring[i].buf = 0;
 347
 348#ifdef CONFIG_TULIP_FIX_DAVICOM
 349        tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
 350#else
 351                tx_ring[i].next = 0;
 352#endif
 353        }
 354
 355        rxRingSize = NUM_RX_DESC;
 356        txRingSize = NUM_TX_DESC;
 357
 358        /* Write the end of list marker to the descriptor lists. */
 359        rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
 360        tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
 361
 362        /* Tell the adapter where the TX/RX rings are located. */
 363        OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
 364        OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
 365
 366        START_DE4X5(dev);
 367
 368        tx_new = 0;
 369        rx_new = 0;
 370
 371        send_setup_frame(dev, bis);
 372
 373        return 0;
 374}
 375
 376static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
 377{
 378        int             status = -1;
 379        int             i;
 380
 381        if (length <= 0) {
 382                printf("%s: bad packet size: %d\n", dev->name, length);
 383                goto Done;
 384        }
 385
 386        for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
 387                if (i >= TOUT_LOOP) {
 388                        printf("%s: tx error buffer not ready\n", dev->name);
 389                        goto Done;
 390                }
 391        }
 392
 393        tx_ring[tx_new].buf    = cpu_to_le32(phys_to_bus((u32) packet));
 394        tx_ring[tx_new].des1   = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
 395        tx_ring[tx_new].status = cpu_to_le32(T_OWN);
 396
 397        OUTL(dev, POLL_DEMAND, DE4X5_TPD);
 398
 399        for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
 400                if (i >= TOUT_LOOP) {
 401                        printf(".%s: tx buffer not ready\n", dev->name);
 402                        goto Done;
 403                }
 404        }
 405
 406        if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
 407#if 0 /* test-only */
 408                printf("TX error status = 0x%08X\n",
 409                        le32_to_cpu(tx_ring[tx_new].status));
 410#endif
 411                tx_ring[tx_new].status = 0x0;
 412                goto Done;
 413        }
 414
 415        status = length;
 416
 417 Done:
 418    tx_new = (tx_new+1) % NUM_TX_DESC;
 419        return status;
 420}
 421
 422static int dc21x4x_recv(struct eth_device* dev)
 423{
 424        s32             status;
 425        int             length    = 0;
 426
 427        for ( ; ; ) {
 428                status = (s32)le32_to_cpu(rx_ring[rx_new].status);
 429
 430                if (status & R_OWN) {
 431                        break;
 432                }
 433
 434                if (status & RD_LS) {
 435                        /* Valid frame status.
 436                         */
 437                        if (status & RD_ES) {
 438
 439                                /* There was an error.
 440                                 */
 441                                printf("RX error status = 0x%08X\n", status);
 442                        } else {
 443                                /* A valid frame received.
 444                                 */
 445                                length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
 446
 447                                /* Pass the packet up to the protocol
 448                                 * layers.
 449                                 */
 450                                net_process_received_packet(
 451                                        net_rx_packets[rx_new], length - 4);
 452                        }
 453
 454                        /* Change buffer ownership for this frame, back
 455                         * to the adapter.
 456                         */
 457                        rx_ring[rx_new].status = cpu_to_le32(R_OWN);
 458                }
 459
 460                /* Update entry information.
 461                 */
 462                rx_new = (rx_new + 1) % rxRingSize;
 463        }
 464
 465        return length;
 466}
 467
 468static void dc21x4x_halt(struct eth_device* dev)
 469{
 470        int             devbusfn = (int) dev->priv;
 471
 472        STOP_DE4X5(dev);
 473        OUTL(dev, 0, DE4X5_SICR);
 474
 475        pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
 476}
 477
 478static void send_setup_frame(struct eth_device* dev, bd_t *bis)
 479{
 480        int             i;
 481        char    setup_frame[SETUP_FRAME_LEN];
 482        char    *pa = &setup_frame[0];
 483
 484        memset(pa, 0xff, SETUP_FRAME_LEN);
 485
 486        for (i = 0; i < ETH_ALEN; i++) {
 487                *(pa + (i & 1)) = dev->enetaddr[i];
 488                if (i & 0x01) {
 489                        pa += 4;
 490                }
 491        }
 492
 493        for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
 494                if (i >= TOUT_LOOP) {
 495                        printf("%s: tx error buffer not ready\n", dev->name);
 496                        goto Done;
 497                }
 498        }
 499
 500        tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
 501        tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
 502        tx_ring[tx_new].status = cpu_to_le32(T_OWN);
 503
 504        OUTL(dev, POLL_DEMAND, DE4X5_TPD);
 505
 506        for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
 507                if (i >= TOUT_LOOP) {
 508                        printf("%s: tx buffer not ready\n", dev->name);
 509                        goto Done;
 510                }
 511        }
 512
 513        if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
 514                printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
 515        }
 516        tx_new = (tx_new+1) % NUM_TX_DESC;
 517
 518Done:
 519        return;
 520}
 521
 522#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
 523/* SROM Read and write routines.
 524 */
 525static void
 526sendto_srom(struct eth_device* dev, u_int command, u_long addr)
 527{
 528        OUTL(dev, command, addr);
 529        udelay(1);
 530}
 531
 532static int
 533getfrom_srom(struct eth_device* dev, u_long addr)
 534{
 535        s32 tmp;
 536
 537        tmp = INL(dev, addr);
 538        udelay(1);
 539
 540        return tmp;
 541}
 542
 543/* Note: this routine returns extra data bits for size detection. */
 544static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
 545{
 546        int i;
 547        unsigned retval = 0;
 548        int read_cmd = location | (SROM_READ_CMD << addr_len);
 549
 550        sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 551        sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 552
 553#ifdef DEBUG_SROM
 554        printf(" EEPROM read at %d ", location);
 555#endif
 556
 557        /* Shift the read command bits out. */
 558        for (i = 4 + addr_len; i >= 0; i--) {
 559                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 560                sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
 561                udelay(10);
 562                sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
 563                udelay(10);
 564#ifdef DEBUG_SROM2
 565                printf("%X", getfrom_srom(dev, ioaddr) & 15);
 566#endif
 567                retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
 568        }
 569
 570        sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 571
 572#ifdef DEBUG_SROM2
 573        printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
 574#endif
 575
 576        for (i = 16; i > 0; i--) {
 577                sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 578                udelay(10);
 579#ifdef DEBUG_SROM2
 580                printf("%X", getfrom_srom(dev, ioaddr) & 15);
 581#endif
 582                retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
 583                sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 584                udelay(10);
 585        }
 586
 587        /* Terminate the EEPROM access. */
 588        sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 589
 590#ifdef DEBUG_SROM2
 591        printf(" EEPROM value at %d is %5.5x.\n", location, retval);
 592#endif
 593
 594        return retval;
 595}
 596#endif  /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 597
 598/* This executes a generic EEPROM command, typically a write or write
 599 * enable. It returns the data output from the EEPROM, and thus may
 600 * also be used for reads.
 601 */
 602#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
 603static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
 604{
 605        unsigned retval = 0;
 606
 607#ifdef DEBUG_SROM
 608        printf(" EEPROM op 0x%x: ", cmd);
 609#endif
 610
 611        sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 612
 613        /* Shift the command bits out. */
 614        do {
 615                short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
 616                sendto_srom(dev,dataval, ioaddr);
 617                udelay(10);
 618
 619#ifdef DEBUG_SROM2
 620                printf("%X", getfrom_srom(dev,ioaddr) & 15);
 621#endif
 622
 623                sendto_srom(dev,dataval | DT_CLK, ioaddr);
 624                udelay(10);
 625                retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
 626        } while (--cmd_len >= 0);
 627        sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
 628
 629        /* Terminate the EEPROM access. */
 630        sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
 631
 632#ifdef DEBUG_SROM
 633        printf(" EEPROM result is 0x%5.5x.\n", retval);
 634#endif
 635
 636        return retval;
 637}
 638#endif  /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 639
 640#ifndef CONFIG_TULIP_FIX_DAVICOM
 641static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
 642{
 643        int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
 644
 645        return do_eeprom_cmd(dev, ioaddr,
 646                             (((SROM_READ_CMD << ee_addr_size) | index) << 16)
 647                             | 0xffff, 3 + ee_addr_size + 16);
 648}
 649#endif  /* CONFIG_TULIP_FIX_DAVICOM */
 650
 651#ifdef UPDATE_SROM
 652static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
 653{
 654        int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
 655        int i;
 656        unsigned short newval;
 657
 658        udelay(10*1000); /* test-only */
 659
 660#ifdef DEBUG_SROM
 661        printf("ee_addr_size=%d.\n", ee_addr_size);
 662        printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
 663#endif
 664
 665        /* Enable programming modes. */
 666        do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
 667
 668        /* Do the actual write. */
 669        do_eeprom_cmd(dev, ioaddr,
 670                      (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
 671                      3 + ee_addr_size + 16);
 672
 673        /* Poll for write finished. */
 674        sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 675        for (i = 0; i < 10000; i++)                     /* Typical 2000 ticks */
 676                if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
 677                        break;
 678
 679#ifdef DEBUG_SROM
 680        printf(" Write finished after %d ticks.\n", i);
 681#endif
 682
 683        /* Disable programming. */
 684        do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
 685
 686        /* And read the result. */
 687        newval = do_eeprom_cmd(dev, ioaddr,
 688                               (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
 689                               | 0xffff, 3 + ee_addr_size + 16);
 690#ifdef DEBUG_SROM
 691        printf("  New value at offset %d is %4.4x.\n", index, newval);
 692#endif
 693        return 1;
 694}
 695#endif
 696
 697#ifndef CONFIG_TULIP_FIX_DAVICOM
 698static void read_hw_addr(struct eth_device *dev, bd_t *bis)
 699{
 700        u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
 701        int i, j = 0;
 702
 703        for (i = 0; i < (ETH_ALEN >> 1); i++) {
 704                tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
 705                *p = le16_to_cpu(tmp);
 706                j += *p++;
 707        }
 708
 709        if ((j == 0) || (j == 0x2fffd)) {
 710                memset (dev->enetaddr, 0, ETH_ALEN);
 711                debug ("Warning: can't read HW address from SROM.\n");
 712                goto Done;
 713        }
 714
 715        return;
 716
 717Done:
 718#ifdef UPDATE_SROM
 719        update_srom(dev, bis);
 720#endif
 721        return;
 722}
 723#endif  /* CONFIG_TULIP_FIX_DAVICOM */
 724
 725#ifdef UPDATE_SROM
 726static void update_srom(struct eth_device *dev, bd_t *bis)
 727{
 728        int i;
 729        static unsigned short eeprom[0x40] = {
 730                0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
 731                0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
 732                0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
 733                0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
 734                0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
 735                0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
 736                0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
 737                0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
 738                0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
 739                0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
 740                0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
 741                0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
 742                0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
 743                0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
 744                0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
 745                0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
 746        };
 747        uchar enetaddr[6];
 748
 749        /* Ethernet Addr... */
 750        if (!eth_env_get_enetaddr("ethaddr", enetaddr))
 751                return;
 752        eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
 753        eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
 754        eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
 755
 756        for (i=0; i<0x40; i++) {
 757                write_srom(dev, DE4X5_APROM, i, eeprom[i]);
 758        }
 759}
 760#endif  /* UPDATE_SROM */
 761