1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017 NXP 4 */ 5 6#ifndef __LS1088A_RDB_H 7#define __LS1088A_RDB_H 8 9#include "ls1088a_common.h" 10 11#if defined(CONFIG_QSPI_BOOT) 12#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 13#define CONFIG_ENV_SECT_SIZE 0x40000 14#elif defined(CONFIG_SD_BOOT) 15#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 16#define CONFIG_SYS_MMC_ENV_DEV 0 17#define CONFIG_ENV_SIZE 0x2000 18#else 19#define CONFIG_ENV_IS_IN_FLASH 20#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 21#define CONFIG_ENV_SECT_SIZE 0x20000 22#define CONFIG_ENV_SIZE 0x20000 23#endif 24 25#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 26#ifndef CONFIG_SPL_BUILD 27#define CONFIG_QIXIS_I2C_ACCESS 28#endif 29#define SYS_NO_FLASH 30#undef CONFIG_CMD_IMLS 31#endif 32 33#define CONFIG_SYS_CLK_FREQ 100000000 34#define CONFIG_DDR_CLK_FREQ 100000000 35#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 36#define COUNTER_FREQUENCY 25000000 /* 25MHz */ 37 38#define CONFIG_DDR_SPD 39#ifdef CONFIG_EMU 40#define CONFIG_SYS_FSL_DDR_EMU 41#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 42#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 43#else 44#define CONFIG_DDR_ECC 45#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47#endif 48#define SPD_EEPROM_ADDRESS 0x51 49#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 50#define CONFIG_DIMM_SLOTS_PER_CTLR 1 51 52 53#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 54#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 55#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 56#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 57 58#define CONFIG_SYS_NOR0_CSPR \ 59 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 60 CSPR_PORT_SIZE_16 | \ 61 CSPR_MSEL_NOR | \ 62 CSPR_V) 63#define CONFIG_SYS_NOR0_CSPR_EARLY \ 64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 65 CSPR_PORT_SIZE_16 | \ 66 CSPR_MSEL_NOR | \ 67 CSPR_V) 68#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 69#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 70 FTIM0_NOR_TEADC(0x1) | \ 71 FTIM0_NOR_TEAHC(0x1)) 72#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 73 FTIM1_NOR_TRAD_NOR(0x1)) 74#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 75 FTIM2_NOR_TCH(0x0) | \ 76 FTIM2_NOR_TWP(0x1)) 77#define CONFIG_SYS_NOR_FTIM3 0x04000000 78#define CONFIG_SYS_IFC_CCR 0x01000000 79 80#ifndef SYS_NO_FLASH 81#define CONFIG_SYS_FLASH_QUIET_TEST 82#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 83 84#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 85#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 86#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 87#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 88 89#define CONFIG_SYS_FLASH_EMPTY_INFO 90#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 91#endif 92#endif 93 94#ifndef SPL_NO_IFC 95#define CONFIG_NAND_FSL_IFC 96#endif 97 98#define CONFIG_SYS_NAND_MAX_ECCPOS 256 99#define CONFIG_SYS_NAND_MAX_OOBFREE 2 100 101#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 102#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 103 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 104 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 105 | CSPR_V) 106#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 107 108#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 109 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 110 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 111 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 112 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 113 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 114 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 115 116#define CONFIG_SYS_NAND_ONFI_DETECTION 117 118/* ONFI NAND Flash mode0 Timing Params */ 119#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 120 FTIM0_NAND_TWP(0x18) | \ 121 FTIM0_NAND_TWCHT(0x07) | \ 122 FTIM0_NAND_TWH(0x0a)) 123#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 124 FTIM1_NAND_TWBE(0x39) | \ 125 FTIM1_NAND_TRR(0x0e) | \ 126 FTIM1_NAND_TRP(0x18)) 127#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 128 FTIM2_NAND_TREH(0x0a) | \ 129 FTIM2_NAND_TWHRE(0x1e)) 130#define CONFIG_SYS_NAND_FTIM3 0x0 131 132#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 133#define CONFIG_SYS_MAX_NAND_DEVICE 1 134#define CONFIG_MTD_NAND_VERIFY_WRITE 135#define CONFIG_CMD_NAND 136 137#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 138 139#ifndef SPL_NO_QIXIS 140#define CONFIG_FSL_QIXIS 141#endif 142 143#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 144#define QIXIS_BRDCFG4_OFFSET 0x54 145#define QIXIS_LBMAP_SWITCH 2 146#define QIXIS_QMAP_MASK 0xe0 147#define QIXIS_QMAP_SHIFT 5 148#define QIXIS_LBMAP_MASK 0x1f 149#define QIXIS_LBMAP_SHIFT 5 150#define QIXIS_LBMAP_DFLTBANK 0x00 151#define QIXIS_LBMAP_ALTBANK 0x20 152#define QIXIS_LBMAP_SD 0x00 153#define QIXIS_LBMAP_EMMC 0x00 154#define QIXIS_LBMAP_SD_QSPI 0x00 155#define QIXIS_LBMAP_QSPI 0x00 156#define QIXIS_RCW_SRC_SD 0x40 157#define QIXIS_RCW_SRC_EMMC 0x41 158#define QIXIS_RCW_SRC_QSPI 0x62 159#define QIXIS_RST_CTL_RESET 0x31 160#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 161#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 162#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 163#define QIXIS_RST_FORCE_MEM 0x01 164 165#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 166#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 167 | CSPR_PORT_SIZE_8 \ 168 | CSPR_MSEL_GPCM \ 169 | CSPR_V) 170#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 171 | CSPR_PORT_SIZE_8 \ 172 | CSPR_MSEL_GPCM \ 173 | CSPR_V) 174 175#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 176#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 177/* QIXIS Timing parameters*/ 178#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 179 FTIM0_GPCM_TEADC(0x0e) | \ 180 FTIM0_GPCM_TEAHC(0x0e)) 181#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 182 FTIM1_GPCM_TRAD(0x3f)) 183#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 184 FTIM2_GPCM_TCH(0xf) | \ 185 FTIM2_GPCM_TWP(0x3E)) 186#define SYS_FPGA_CS_FTIM3 0x0 187 188#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 189#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 190#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 191#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 192#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 193#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 194#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 195#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 196#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 197#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 198#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 199#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 200#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 201#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 202#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 203#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 204#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 205#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 206#else 207#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 208#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 209#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 210#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 211#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 212#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 213#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 214#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 215#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 216#endif 217 218 219#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 220 221#define I2C_MUX_CH_VOL_MONITOR 0xA 222/* Voltage monitor on channel 2*/ 223#define I2C_VOL_MONITOR_ADDR 0x63 224#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 225#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 226#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 227#define I2C_SVDD_MONITOR_ADDR 0x4F 228 229#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" 230#define CONFIG_VID 231 232/* The lowest and highest voltage allowed for LS1088ARDB */ 233#define VDD_MV_MIN 819 234#define VDD_MV_MAX 1212 235 236#define CONFIG_VOL_MONITOR_LTC3882_SET 237#define CONFIG_VOL_MONITOR_LTC3882_READ 238 239/* PM Bus commands code for LTC3882*/ 240#define PMBUS_CMD_PAGE 0x0 241#define PMBUS_CMD_READ_VOUT 0x8B 242#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 243#define PMBUS_CMD_VOUT_COMMAND 0x21 244 245#define PWM_CHANNEL0 0x0 246 247/* 248 * I2C bus multiplexer 249 */ 250#define I2C_MUX_PCA_ADDR_PRI 0x77 251#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 252#define I2C_RETIMER_ADDR 0x18 253#define I2C_MUX_CH_DEFAULT 0x8 254#define I2C_MUX_CH5 0xD 255 256#ifndef SPL_NO_RTC 257/* 258* RTC configuration 259*/ 260#define RTC 261#define CONFIG_RTC_PCF8563 1 262#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 263#define CONFIG_CMD_DATE 264#endif 265 266/* EEPROM */ 267#define CONFIG_ID_EEPROM 268#define CONFIG_SYS_I2C_EEPROM_NXID 269#define CONFIG_SYS_EEPROM_BUS_NUM 0 270#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 271#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 272#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 273#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 274 275#ifndef SPL_NO_QSPI 276/* QSPI device */ 277#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 278#define FSL_QSPI_FLASH_SIZE (1 << 26) 279#define FSL_QSPI_FLASH_NUM 2 280#endif 281#endif 282 283#define CONFIG_CMD_MEMINFO 284#define CONFIG_SYS_MEMTEST_START 0x80000000 285#define CONFIG_SYS_MEMTEST_END 0x9fffffff 286 287#ifdef CONFIG_SPL_BUILD 288#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 289#else 290#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 291#endif 292 293#define CONFIG_FSL_MEMAC 294 295#ifndef SPL_NO_ENV 296/* Initial environment variables */ 297#if defined(CONFIG_QSPI_BOOT) 298#define MC_INIT_CMD \ 299 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 300 "sf read 0x80100000 0xE00000 0x100000;" \ 301 "env exists secureboot && " \ 302 "sf read 0x80700000 0x700000 0x40000 && " \ 303 "sf read 0x80740000 0x740000 0x40000 && " \ 304 "esbc_validate 0x80700000 && " \ 305 "esbc_validate 0x80740000 ;" \ 306 "fsl_mc start mc 0x80000000 0x80100000\0" \ 307 "mcmemsize=0x70000000\0" 308#elif defined(CONFIG_SD_BOOT) 309#define MC_INIT_CMD \ 310 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 311 "mmc read 0x80100000 0x7000 0x800;" \ 312 "env exists secureboot && " \ 313 "mmc read 0x80700000 0x3800 0x10 && " \ 314 "mmc read 0x80740000 0x3A00 0x10 && " \ 315 "esbc_validate 0x80700000 && " \ 316 "esbc_validate 0x80740000 ;" \ 317 "fsl_mc start mc 0x80000000 0x80100000\0" \ 318 "mcmemsize=0x70000000\0" 319#endif 320 321#undef CONFIG_EXTRA_ENV_SETTINGS 322#define CONFIG_EXTRA_ENV_SETTINGS \ 323 "BOARD=ls1088ardb\0" \ 324 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 325 "ramdisk_addr=0x800000\0" \ 326 "ramdisk_size=0x2000000\0" \ 327 "fdt_high=0xa0000000\0" \ 328 "initrd_high=0xffffffffffffffff\0" \ 329 "fdt_addr=0x64f00000\0" \ 330 "kernel_addr=0x1000000\0" \ 331 "kernel_addr_sd=0x8000\0" \ 332 "kernelhdr_addr_sd=0x4000\0" \ 333 "kernel_start=0x580100000\0" \ 334 "kernelheader_start=0x580800000\0" \ 335 "scriptaddr=0x80000000\0" \ 336 "scripthdraddr=0x80080000\0" \ 337 "fdtheader_addr_r=0x80100000\0" \ 338 "kernelheader_addr=0x800000\0" \ 339 "kernelheader_addr_r=0x80200000\0" \ 340 "kernel_addr_r=0x81000000\0" \ 341 "kernelheader_size=0x40000\0" \ 342 "fdt_addr_r=0x90000000\0" \ 343 "load_addr=0xa0000000\0" \ 344 "kernel_size=0x2800000\0" \ 345 "kernel_size_sd=0x14000\0" \ 346 "kernelhdr_size_sd=0x10\0" \ 347 MC_INIT_CMD \ 348 BOOTENV \ 349 "boot_scripts=ls1088ardb_boot.scr\0" \ 350 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 351 "scan_dev_for_boot_part=" \ 352 "part list ${devtype} ${devnum} devplist; " \ 353 "env exists devplist || setenv devplist 1; " \ 354 "for distro_bootpart in ${devplist}; do " \ 355 "if fstype ${devtype} " \ 356 "${devnum}:${distro_bootpart} " \ 357 "bootfstype; then " \ 358 "run scan_dev_for_boot; " \ 359 "fi; " \ 360 "done\0" \ 361 "scan_dev_for_boot=" \ 362 "echo Scanning ${devtype} " \ 363 "${devnum}:${distro_bootpart}...; " \ 364 "for prefix in ${boot_prefixes}; do " \ 365 "run scan_dev_for_scripts; " \ 366 "done;\0" \ 367 "boot_a_script=" \ 368 "load ${devtype} ${devnum}:${distro_bootpart} " \ 369 "${scriptaddr} ${prefix}${script}; " \ 370 "env exists secureboot && load ${devtype} " \ 371 "${devnum}:${distro_bootpart} " \ 372 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 373 "&& esbc_validate ${scripthdraddr};" \ 374 "source ${scriptaddr}\0" \ 375 "installer=load mmc 0:2 $load_addr " \ 376 "/flex_installer_arm64.itb; " \ 377 "env exists mcinitcmd && run mcinitcmd && " \ 378 "mmc read 0x80001000 0x6800 0x800;" \ 379 "fsl_mc lazyapply dpl 0x80001000;" \ 380 "bootm $load_addr#ls1088ardb\0" \ 381 "qspi_bootcmd=echo Trying load from qspi..;" \ 382 "sf probe && sf read $load_addr " \ 383 "$kernel_addr $kernel_size ; env exists secureboot " \ 384 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 385 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 386 "bootm $load_addr#$BOARD\0" \ 387 "sd_bootcmd=echo Trying load from sd card..;" \ 388 "mmcinfo; mmc read $load_addr " \ 389 "$kernel_addr_sd $kernel_size_sd ;" \ 390 "env exists secureboot && mmc read $kernelheader_addr_r "\ 391 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 392 " && esbc_validate ${kernelheader_addr_r};" \ 393 "bootm $load_addr#$BOARD\0" 394 395#undef CONFIG_BOOTCOMMAND 396#if defined(CONFIG_QSPI_BOOT) 397/* Try to boot an on-QSPI kernel first, then do normal distro boot */ 398#define CONFIG_BOOTCOMMAND \ 399 "sf read 0x80001000 0xd00000 0x100000;" \ 400 "env exists mcinitcmd && env exists secureboot " \ 401 " && sf read 0x80780000 0x780000 0x100000 " \ 402 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 403 "&& fsl_mc lazyapply dpl 0x80001000;" \ 404 "run distro_bootcmd;run qspi_bootcmd;" \ 405 "env exists secureboot && esbc_halt;" 406 407/* Try to boot an on-SD kernel first, then do normal distro boot */ 408#elif defined(CONFIG_SD_BOOT) 409#define CONFIG_BOOTCOMMAND \ 410 "env exists mcinitcmd && mmcinfo; " \ 411 "mmc read 0x80001000 0x6800 0x800; " \ 412 "env exists mcinitcmd && env exists secureboot " \ 413 " && mmc read 0x80780000 0x3C00 0x10 " \ 414 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 415 "&& fsl_mc lazyapply dpl 0x80001000;" \ 416 "run distro_bootcmd;run sd_bootcmd;" \ 417 "env exists secureboot && esbc_halt;" 418#endif 419 420/* MAC/PHY configuration */ 421#ifdef CONFIG_FSL_MC_ENET 422#define CONFIG_PHYLIB 423 424#define CONFIG_PHY_VITESSE 425#define AQ_PHY_ADDR1 0x00 426#define AQR105_IRQ_MASK 0x00000004 427 428#define QSGMII1_PORT1_PHY_ADDR 0x0c 429#define QSGMII1_PORT2_PHY_ADDR 0x0d 430#define QSGMII1_PORT3_PHY_ADDR 0x0e 431#define QSGMII1_PORT4_PHY_ADDR 0x0f 432#define QSGMII2_PORT1_PHY_ADDR 0x1c 433#define QSGMII2_PORT2_PHY_ADDR 0x1d 434#define QSGMII2_PORT3_PHY_ADDR 0x1e 435#define QSGMII2_PORT4_PHY_ADDR 0x1f 436 437#define CONFIG_ETHPRIME "DPMAC1@xgmii" 438#define CONFIG_PHY_GIGE 439#endif 440#endif 441 442/* MMC */ 443#ifdef CONFIG_MMC 444#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 445#endif 446 447#ifndef SPL_NO_ENV 448 449#define BOOT_TARGET_DEVICES(func) \ 450 func(MMC, mmc, 0) \ 451 func(SCSI, scsi, 0) 452#include <config_distro_bootcmd.h> 453#endif 454 455#include <asm/fsl_secure_boot.h> 456 457#endif /* __LS1088A_RDB_H */ 458