LXR uboot/include/configs/mx53ppd.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4 * Jason Liu <r64343@freescale.com>
   5 *
   6 * Configuration settings for Freescale MX53 low cost board.
   7 */
   8
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12#include <asm/arch/imx-regs.h>
  13
  14#define CONSOLE_DEV     "ttymxc0"
  15
  16#define CONFIG_CMDLINE_TAG
  17#define CONFIG_SETUP_MEMORY_TAGS
  18#define CONFIG_INITRD_TAG
  19
  20#define CONFIG_SYS_FSL_CLK
  21
  22/* Size of malloc() pool */
  23#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
  24
  25#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
  26
  27#define CONFIG_BOARD_LATE_INIT
  28#define CONFIG_REVISION_TAG
  29
  30#define CONFIG_MXC_UART
  31#define CONFIG_MXC_UART_BASE    UART1_BASE
  32
  33/* MMC Configs */
  34#define CONFIG_SYS_FSL_ESDHC_ADDR       0
  35#define CONFIG_SYS_FSL_ESDHC_NUM        2
  36
  37/* Eth Configs */
  38
  39#define CONFIG_FEC_MXC
  40#define IMX_FEC_BASE    FEC_BASE_ADDR
  41#define CONFIG_FEC_MXC_PHYADDR  0x1F
  42
  43/* USB Configs */
  44#define CONFIG_USB_EHCI_MX5
  45#define CONFIG_USB_HOST_ETHER
  46#define CONFIG_USB_ETHER_ASIX
  47#define CONFIG_USB_ETHER_MCS7830
  48#define CONFIG_USB_ETHER_SMSC95XX
  49#define CONFIG_MXC_USB_PORT     1
  50#define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
  51#define CONFIG_MXC_USB_FLAGS    0
  52
  53#define CONFIG_SYS_RTC_BUS_NUM          2
  54#define CONFIG_SYS_I2C_RTC_ADDR 0x30
  55
  56/* I2C Configs */
  57#define CONFIG_SYS_I2C
  58#define CONFIG_SYS_I2C_MXC
  59#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  60#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  61#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  62
  63/* PMIC Controller */
  64#define CONFIG_POWER
  65#define CONFIG_POWER_I2C
  66#define CONFIG_DIALOG_POWER
  67#define CONFIG_POWER_FSL
  68#define CONFIG_POWER_FSL_MC13892
  69#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
  70#define CONFIG_SYS_FSL_PMIC_I2C_ADDR    0x8
  71
  72/* allow to overwrite serial and ethaddr */
  73#define CONFIG_ENV_OVERWRITE
  74#define CONFIG_BAUDRATE                 115200
  75
  76/* Command definition */
  77
  78#define CONFIG_ETHPRIME         "FEC0"
  79
  80#define CONFIG_LOADADDR         0x72000000      /* loadaddr env var */
  81
  82#define PPD_CONFIG_NFS \
  83        "nfsserver=192.168.252.95\0" \
  84        "gatewayip=192.168.252.95\0" \
  85        "netmask=255.255.255.0\0" \
  86        "ipaddr=192.168.252.99\0" \
  87        "kernsize=0x2000\0" \
  88        "use_dhcp=0\0" \
  89        "nfsroot=/opt/springdale/rd\0" \
  90        "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
  91                "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
  92        "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
  93                "set getcmd dhcp; else set kern_ipconf " \
  94                "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
  95                "set getcmd tftp; fi\0" \
  96        "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
  97                "${nfsserver}:${image}; bootm ${loadaddr}\0" \
  98
  99#define CONFIG_EXTRA_ENV_SETTINGS \
 100        PPD_CONFIG_NFS \
 101        "image=/boot/fitImage\0" \
 102        "fdt_high=0xffffffff\0" \
 103        "dev=mmc\0" \
 104        "devnum=0\0" \
 105        "rootdev=mmcblk0p\0" \
 106        "quiet=quiet loglevel=0\0" \
 107        "console=" CONSOLE_DEV "\0" \
 108        "lvds=ldb\0" \
 109        "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
 110                "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
 111                "console=${console} ${rtc_status}\0" \
 112        "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
 113                "rootwait ${bootargs}\0" \
 114        "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
 115                "then setenv quiet; fi\0" \
 116        "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
 117                "/boot/bootcause/firstboot\0" \
 118        "swappartitions=setexpr partnum 3 - ${partnum}\0" \
 119        "failbootcmd=" \
 120                "ppd_lcd_enable; " \
 121                "msg=\"Monitor failed to start.  " \
 122                        "Try again, or contact GE Service for support.\"; " \
 123                "echo $msg; " \
 124                "setenv stdout vga; " \
 125                "echo \"\n\n\n\n    \" $msg; " \
 126                "setenv stdout serial; " \
 127                "mw.b 0x7000A000 0xbc; " \
 128                "mw.b 0x7000A001 0x00; " \
 129                "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
 130        "altbootcmd=" \
 131                "run doquiet; " \
 132                "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 133                "run hasfirstboot || setenv partnum 0; " \
 134                "if test ${partnum} != 0; then " \
 135                        "setenv bootcause REVERT; " \
 136                        "run swappartitions loadimage doboot; " \
 137                "fi; " \
 138                "run failbootcmd\0" \
 139        "loadimage=" \
 140                "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 141        "doboot=" \
 142                "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
 143                "run setargs; " \
 144                "run bootargs_emmc; " \
 145                "bootm ${loadaddr}\0" \
 146        "tryboot=" \
 147                "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 148                "run loadimage || run swappartitions && run loadimage || " \
 149                        "setenv partnum 0 && echo MISSING IMAGE;" \
 150                "run doboot; " \
 151                "run failbootcmd\0" \
 152        "video-mode=" \
 153                "lcd:800x480-24@60,monitor=lcd\0" \
 154
 155#define CONFIG_MMCBOOTCOMMAND \
 156        "if mmc dev ${devnum}; then " \
 157                "run doquiet; " \
 158                "run tryboot; " \
 159        "fi; " \
 160
 161#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
 162
 163#define CONFIG_ARP_TIMEOUT      200UL
 164
 165/* Miscellaneous configurable options */
 166#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 167
 168#define CONFIG_SYS_MAXARGS      48      /* max number of command args */
 169#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 170
 171#define CONFIG_SYS_MEMTEST_START       0x70000000
 172#define CONFIG_SYS_MEMTEST_END         0x70010000
 173
 174#define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 175
 176/* Physical Memory Map */
 177#define PHYS_SDRAM_1                    CSD0_BASE_ADDR
 178#define PHYS_SDRAM_1_SIZE               (gd->bd->bi_dram[0].size)
 179#define PHYS_SDRAM_2                    CSD1_BASE_ADDR
 180#define PHYS_SDRAM_2_SIZE               (gd->bd->bi_dram[1].size)
 181#define PHYS_SDRAM_SIZE                 (gd->ram_size)
 182
 183#define CONFIG_SYS_SDRAM_BASE           (PHYS_SDRAM_1)
 184#define CONFIG_SYS_INIT_RAM_ADDR        (IRAM_BASE_ADDR)
 185#define CONFIG_SYS_INIT_RAM_SIZE        (IRAM_SIZE)
 186
 187#define CONFIG_SYS_INIT_SP_OFFSET \
 188        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 189#define CONFIG_SYS_INIT_SP_ADDR \
 190        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 191
 192/* FLASH and environment organization */
 193#define CONFIG_ENV_OFFSET      (12 * 64 * 1024)
 194#define CONFIG_ENV_SIZE        (10 * 1024)
 195#define CONFIG_SYS_MMC_ENV_DEV 0
 196
 197#define CONFIG_CMD_FUSE
 198#define CONFIG_FSL_IIM
 199
 200#define CONFIG_SYS_I2C_SPEED    100000
 201
 202/* I2C1 */
 203#define CONFIG_SYS_NUM_I2C_BUSES        9
 204#define CONFIG_SYS_I2C_MAX_HOPS         1
 205#define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 206                                        {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
 207                                        {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 208                                        {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 209                                        {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
 210                                        {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
 211                                        {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
 212                                        {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
 213                                        {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
 214                                }
 215
 216#define CONFIG_BCH
 217
 218/* Backlight Control */
 219#define CONFIG_PWM_IMX
 220#define CONFIG_IMX6_PWM_PER_CLK 66666000
 221
 222/* Framebuffer and LCD */
 223#ifdef CONFIG_VIDEO
 224        #define CONFIG_VIDEO_IPUV3
 225#endif
 226
 227#endif                          /* __CONFIG_H */
 228