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14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17
18
19
20#define CONFIG_E300 1
21#define CONFIG_MPC834x 1
22#define CONFIG_MPC8349 1
23
24
25#undef CONFIG_MPC83XX_PCI2
26
27
28
29
30
31
32
33#ifdef CONFIG_PCI_33M
34#define CONFIG_83XX_CLKIN 33000000
35#else
36#define CONFIG_83XX_CLKIN 66000000
37#endif
38
39#ifndef CONFIG_SYS_CLK_FREQ
40#ifdef CONFIG_PCI_33M
41#define CONFIG_SYS_CLK_FREQ 33000000
42#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
43#else
44#define CONFIG_SYS_CLK_FREQ 66000000
45#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
46#endif
47#endif
48
49#define CONFIG_SYS_IMMR 0xE0000000
50
51#undef CONFIG_SYS_DRAM_TEST
52#define CONFIG_SYS_MEMTEST_START 0x00000000
53#define CONFIG_SYS_MEMTEST_END 0x00100000
54
55
56
57
58#undef CONFIG_DDR_ECC
59#undef CONFIG_DDR_ECC_CMD
60#define CONFIG_SPD_EEPROM
61#define CONFIG_SYS_83XX_DDR_USES_CS0
62
63
64
65
66
67
68
69
70
71
72
73#undef CONFIG_DDR_32BIT
74
75#define CONFIG_SYS_DDR_BASE 0x00000000
76#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
77#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
78#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
79 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
80#define CONFIG_DDR_2T_TIMING
81
82#if defined(CONFIG_SPD_EEPROM)
83
84
85
86#define SPD_EEPROM_ADDRESS 0x52
87
88#else
89
90
91
92
93#define CONFIG_SYS_DDR_SIZE 256
94#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
95 | CSCONFIG_ROW_BIT_13 \
96 | CSCONFIG_COL_BIT_10)
97#define CONFIG_SYS_DDR_TIMING_1 0x36332321
98#define CONFIG_SYS_DDR_TIMING_2 0x00000800
99#define CONFIG_SYS_DDR_CONTROL 0xc2000000
100#define CONFIG_SYS_DDR_INTERVAL 0x04060100
101
102#if defined(CONFIG_DDR_32BIT)
103
104
105#define CONFIG_SYS_DDR_MODE 0x00000023
106#else
107
108
109#define CONFIG_SYS_DDR_MODE 0x00000022
110#endif
111#endif
112
113
114
115
116#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
117#define CONFIG_SYS_LBC_SDRAM_SIZE 64
118
119
120
121
122#define CONFIG_SYS_FLASH_BASE 0xFF800000
123#define CONFIG_SYS_FLASH_SIZE 8
124
125#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
126 | BR_PS_16 \
127 | BR_MS_GPCM \
128 | BR_V)
129
130#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
131 | OR_GPCM_XAM \
132 | OR_GPCM_CSNT \
133 | OR_GPCM_ACS_DIV2 \
134 | OR_GPCM_XACS \
135 | OR_GPCM_SCY_15 \
136 | OR_GPCM_TRLX_SET \
137 | OR_GPCM_EHTR_SET \
138 | OR_GPCM_EAD)
139
140
141
142#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
143#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
144
145#define CONFIG_SYS_MAX_FLASH_BANKS 1
146#define CONFIG_SYS_MAX_FLASH_SECT 64
147
148#undef CONFIG_SYS_FLASH_CHECKSUM
149#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
150#define CONFIG_SYS_FLASH_WRITE_TOUT 500
151
152#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
153
154#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
155#define CONFIG_SYS_RAMBOOT
156#else
157#undef CONFIG_SYS_RAMBOOT
158#endif
159
160#define CONFIG_SYS_INIT_RAM_LOCK 1
161
162#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
163
164#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
165
166#define CONFIG_SYS_GBL_DATA_OFFSET \
167 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
168#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
169
170#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
171#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
172
173
174
175
176
177
178
179#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
180#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
181#define CONFIG_SYS_LBC_LBCR 0x00000000
182
183#undef CONFIG_SYS_LB_SDRAM
184
185#ifdef CONFIG_SYS_LB_SDRAM
186
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200
201
202#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
203 | BR_PS_32 \
204 | BR_MS_SDRAM \
205 | BR_V)
206
207#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
208#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
209
210
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214
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221
222
223
224#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
225 | OR_SDRAM_XAM \
226 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
227 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
228 | OR_SDRAM_EAD)
229
230
231
232#define CONFIG_SYS_LBC_LSRT 0x32000000
233
234#define CONFIG_SYS_LBC_MRTPR 0x20000000
235
236#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
237 | LSDMR_BSMA1516 \
238 | LSDMR_RFCR8 \
239 | LSDMR_PRETOACT6 \
240 | LSDMR_ACTTORW3 \
241 | LSDMR_BL8 \
242 | LSDMR_WRC3 \
243 | LSDMR_CL3)
244
245
246
247
248#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
249#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
250#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
251#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
252#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
253#endif
254
255
256
257
258#define CONFIG_SYS_NS16550_SERIAL
259#define CONFIG_SYS_NS16550_REG_SIZE 1
260#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
261
262#define CONFIG_SYS_BAUDRATE_TABLE \
263 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
264
265#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
266#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
267
268
269#define CONFIG_SYS_I2C
270#define CONFIG_SYS_I2C_FSL
271#define CONFIG_SYS_FSL_I2C_SPEED 400000
272#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
273#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
274#define CONFIG_SYS_FSL_I2C2_SPEED 400000
275#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
276#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
277#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
278
279
280
281#define CONFIG_SYS_TSEC1_OFFSET 0x24000
282#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
283#define CONFIG_SYS_TSEC2_OFFSET 0x25000
284#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
285
286
287
288
289
290#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
291#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
292#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
293#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
294#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
295#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
296#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
297#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
298#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
299
300#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
301#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
302#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
303#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
304#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
305#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
306#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
307#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
308#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
309
310#if defined(CONFIG_PCI)
311
312#define PCI_64BIT
313#define PCI_ONE_PCI1
314#if defined(PCI_64BIT)
315#undef PCI_ALL_PCI1
316#undef PCI_TWO_PCI1
317#undef PCI_ONE_PCI1
318#endif
319
320#undef CONFIG_EEPRO100
321#undef CONFIG_TULIP
322
323#if !defined(CONFIG_PCI_PNP)
324 #define PCI_ENET0_IOADDR 0xFIXME
325 #define PCI_ENET0_MEMADDR 0xFIXME
326 #define PCI_IDSEL_NUMBER 0xFIXME
327#endif
328
329#undef CONFIG_PCI_SCAN_SHOW
330#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
331
332#endif
333
334
335
336
337
338#if defined(CONFIG_TSEC_ENET)
339
340#define CONFIG_TSEC1 1
341#define CONFIG_TSEC1_NAME "TSEC0"
342#define CONFIG_TSEC2 1
343#define CONFIG_TSEC2_NAME "TSEC1"
344#define CONFIG_PHY_BCM5421S 1
345#define TSEC1_PHY_ADDR 0x19
346#define TSEC2_PHY_ADDR 0x1a
347#define TSEC1_PHYIDX 0
348#define TSEC2_PHYIDX 0
349#define TSEC1_FLAGS TSEC_GIGABIT
350#define TSEC2_FLAGS TSEC_GIGABIT
351
352
353#define CONFIG_ETHPRIME "TSEC0"
354
355#endif
356
357
358
359
360#ifndef CONFIG_SYS_RAMBOOT
361 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
362 #define CONFIG_ENV_SECT_SIZE 0x20000
363 #define CONFIG_ENV_SIZE 0x2000
364
365
366#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
367#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
368
369#else
370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
371 #define CONFIG_ENV_SIZE 0x2000
372#endif
373
374#define CONFIG_LOADS_ECHO 1
375#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
376
377
378
379
380#define CONFIG_BOOTP_BOOTFILESIZE
381
382
383
384
385
386#undef CONFIG_WATCHDOG
387
388
389
390
391#define CONFIG_SYS_LOAD_ADDR 0x2000000
392
393
394
395
396
397
398
399#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
400
401#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
402
403#if 1
404#define CONFIG_SYS_HRCW_LOW (\
405 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
406 HRCWL_DDR_TO_SCB_CLK_1X1 |\
407 HRCWL_CSB_TO_CLKIN |\
408 HRCWL_VCO_1X2 |\
409 HRCWL_CORE_TO_CSB_2X1)
410#elif 0
411#define CONFIG_SYS_HRCW_LOW (\
412 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
413 HRCWL_DDR_TO_SCB_CLK_1X1 |\
414 HRCWL_CSB_TO_CLKIN |\
415 HRCWL_VCO_1X4 |\
416 HRCWL_CORE_TO_CSB_3X1)
417#elif 0
418#define CONFIG_SYS_HRCW_LOW (\
419 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
420 HRCWL_DDR_TO_SCB_CLK_1X1 |\
421 HRCWL_CSB_TO_CLKIN |\
422 HRCWL_VCO_1X4 |\
423 HRCWL_CORE_TO_CSB_2X1)
424#elif 0
425#define CONFIG_SYS_HRCW_LOW (\
426 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
427 HRCWL_DDR_TO_SCB_CLK_1X1 |\
428 HRCWL_CSB_TO_CLKIN |\
429 HRCWL_VCO_1X4 |\
430 HRCWL_CORE_TO_CSB_1X1)
431#elif 0
432#define CONFIG_SYS_HRCW_LOW (\
433 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
434 HRCWL_DDR_TO_SCB_CLK_1X1 |\
435 HRCWL_CSB_TO_CLKIN |\
436 HRCWL_VCO_1X4 |\
437 HRCWL_CORE_TO_CSB_1X1)
438#endif
439
440#if defined(PCI_64BIT)
441#define CONFIG_SYS_HRCW_HIGH (\
442 HRCWH_PCI_HOST |\
443 HRCWH_64_BIT_PCI |\
444 HRCWH_PCI1_ARBITER_ENABLE |\
445 HRCWH_PCI2_ARBITER_DISABLE |\
446 HRCWH_CORE_ENABLE |\
447 HRCWH_FROM_0X00000100 |\
448 HRCWH_BOOTSEQ_DISABLE |\
449 HRCWH_SW_WATCHDOG_DISABLE |\
450 HRCWH_ROM_LOC_LOCAL_16BIT |\
451 HRCWH_TSEC1M_IN_GMII |\
452 HRCWH_TSEC2M_IN_GMII)
453#else
454#define CONFIG_SYS_HRCW_HIGH (\
455 HRCWH_PCI_HOST |\
456 HRCWH_32_BIT_PCI |\
457 HRCWH_PCI1_ARBITER_ENABLE |\
458 HRCWH_PCI2_ARBITER_ENABLE |\
459 HRCWH_CORE_ENABLE |\
460 HRCWH_FROM_0X00000100 |\
461 HRCWH_BOOTSEQ_DISABLE |\
462 HRCWH_SW_WATCHDOG_DISABLE |\
463 HRCWH_ROM_LOC_LOCAL_16BIT |\
464 HRCWH_TSEC1M_IN_GMII |\
465 HRCWH_TSEC2M_IN_GMII)
466#endif
467
468
469#define CONFIG_SYS_SICRH 0
470#define CONFIG_SYS_SICRL SICRL_LDP_A
471
472#define CONFIG_SYS_HID0_INIT 0x000000000
473#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
474 | HID0_ENABLE_INSTRUCTION_CACHE)
475
476
477
478
479
480
481#define CONFIG_SYS_HID2 HID2_HBE
482
483#define CONFIG_HIGH_BATS 1
484
485
486#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
487 | BATL_PP_RW \
488 | BATL_MEMCOHERENCE)
489#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
490 | BATU_BL_256M \
491 | BATU_VS \
492 | BATU_VP)
493
494
495#ifdef CONFIG_PCI
496#define CONFIG_PCI_INDIRECT_BRIDGE
497#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
498 | BATL_PP_RW \
499 | BATL_MEMCOHERENCE)
500#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
501 | BATU_BL_256M \
502 | BATU_VS \
503 | BATU_VP)
504#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
505 | BATL_PP_RW \
506 | BATL_CACHEINHIBIT \
507 | BATL_GUARDEDSTORAGE)
508#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
509 | BATU_BL_256M \
510 | BATU_VS \
511 | BATU_VP)
512#else
513#define CONFIG_SYS_IBAT1L (0)
514#define CONFIG_SYS_IBAT1U (0)
515#define CONFIG_SYS_IBAT2L (0)
516#define CONFIG_SYS_IBAT2U (0)
517#endif
518
519#ifdef CONFIG_MPC83XX_PCI2
520#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
521 | BATL_PP_RW \
522 | BATL_MEMCOHERENCE)
523#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
524 | BATU_BL_256M \
525 | BATU_VS \
526 | BATU_VP)
527#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
528 | BATL_PP_RW \
529 | BATL_CACHEINHIBIT \
530 | BATL_GUARDEDSTORAGE)
531#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
532 | BATU_BL_256M \
533 | BATU_VS \
534 | BATU_VP)
535#else
536#define CONFIG_SYS_IBAT3L (0)
537#define CONFIG_SYS_IBAT3U (0)
538#define CONFIG_SYS_IBAT4L (0)
539#define CONFIG_SYS_IBAT4U (0)
540#endif
541
542
543#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
544 | BATL_PP_RW \
545 | BATL_CACHEINHIBIT \
546 | BATL_GUARDEDSTORAGE)
547#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
548 | BATU_BL_256M \
549 | BATU_VS \
550 | BATU_VP)
551
552
553#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
554 | BATL_PP_RW \
555 | BATL_MEMCOHERENCE \
556 | BATL_GUARDEDSTORAGE)
557#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
558 | BATU_BL_256M \
559 | BATU_VS \
560 | BATU_VP)
561
562#define CONFIG_SYS_IBAT7L (0)
563#define CONFIG_SYS_IBAT7U (0)
564
565#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
566#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
567#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
568#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
569#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
570#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
571#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
572#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
573#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
574#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
575#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
576#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
577#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
578#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
579#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
580#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
581
582#if defined(CONFIG_CMD_KGDB)
583#define CONFIG_KGDB_BAUDRATE 230400
584#endif
585
586
587
588
589#define CONFIG_ENV_OVERWRITE
590
591#if defined(CONFIG_TSEC_ENET)
592#define CONFIG_HAS_ETH0
593#define CONFIG_HAS_ETH1
594#endif
595
596#define CONFIG_HOSTNAME "SBC8349"
597#define CONFIG_ROOTPATH "/tftpboot/rootfs"
598#define CONFIG_BOOTFILE "uImage"
599
600
601#define CONFIG_LOADADDR 800000
602
603#define CONFIG_EXTRA_ENV_SETTINGS \
604 "netdev=eth0\0" \
605 "hostname=sbc8349\0" \
606 "nfsargs=setenv bootargs root=/dev/nfs rw " \
607 "nfsroot=${serverip}:${rootpath}\0" \
608 "ramargs=setenv bootargs root=/dev/ram rw\0" \
609 "addip=setenv bootargs ${bootargs} " \
610 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
611 ":${hostname}:${netdev}:off panic=1\0" \
612 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
613 "flash_nfs=run nfsargs addip addtty;" \
614 "bootm ${kernel_addr}\0" \
615 "flash_self=run ramargs addip addtty;" \
616 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
617 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
618 "bootm\0" \
619 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
620 "update=protect off ff800000 ff83ffff; " \
621 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
622 "upd=run load update\0" \
623 "fdtaddr=780000\0" \
624 "fdtfile=sbc8349.dtb\0" \
625 ""
626
627#define CONFIG_NFSBOOTCOMMAND \
628 "setenv bootargs root=/dev/nfs rw " \
629 "nfsroot=$serverip:$rootpath " \
630 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
631 "$netdev:off " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $loadaddr $bootfile;" \
634 "tftp $fdtaddr $fdtfile;" \
635 "bootm $loadaddr - $fdtaddr"
636
637#define CONFIG_RAMBOOTCOMMAND \
638 "setenv bootargs root=/dev/ram rw " \
639 "console=$consoledev,$baudrate $othbootargs;" \
640 "tftp $ramdiskaddr $ramdiskfile;" \
641 "tftp $loadaddr $bootfile;" \
642 "tftp $fdtaddr $fdtfile;" \
643 "bootm $loadaddr $ramdiskaddr $fdtaddr"
644
645#define CONFIG_BOOTCOMMAND "run flash_self"
646
647#endif
648