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7#ifndef _NS87308_H_
8#define _NS87308_H_
9
10#include <asm/pci_io.h>
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12
13
14
15void initialise_ns87308(void);
16
17
18
19
20struct GPIO
21{
22 unsigned char dta1;
23 unsigned char dir1;
24 unsigned char out1;
25 unsigned char puc1;
26 unsigned char dta2;
27 unsigned char dir2;
28 unsigned char out2;
29 unsigned char puc2;
30};
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32
33
34
35#define PWM_FER1 0
36#define PWM_FER2 1
37#define PWM_PMC1 2
38#define PWM_PMC2 3
39#define PWM_PMC3 4
40#define PWM_WDTO 5
41#define PWM_WDCF 6
42#define PWM_WDST 7
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51
52
53#define IO_INDEX_OFFSET_0x 0x0279
54#define IO_INDEX_OFFSET_10 0x015C
55#define IO_INDEX_OFFSET_11 0x002E
56#define IO_DATA_OFFSET_0x 0x0A79
57#define IO_DATA_OFFSET_10 0x015D
58#define IO_DATA_OFFSET_11 0x002F
59
60#if defined(CONFIG_SYS_NS87308_BADDR_0x)
61#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
62#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
63#elif defined(CONFIG_SYS_NS87308_BADDR_10)
64#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
65#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
66#elif defined(CONFIG_SYS_NS87308_BADDR_11)
67#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
68#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
69#endif
70
71
72
73#define SET_RD_DATA_PORT 0x00
74#define SERIAL_ISOLATION 0x01
75#define CONFIG_CONTROL 0x02
76#define WAKE_CSN 0x03
77#define RES_DATA 0x04
78#define STATUS 0x05
79#define SET_CSN 0x06
80#define LOGICAL_DEVICE 0x07
81
82
83#define SID_REG 0x20
84#define SUPOERIO_CONF1 0x21
85#define SUPOERIO_CONF2 0x22
86#define PGCS_INDEX 0x23
87#define PGCS_DATA 0x24
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89
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91
92
93
94#define ACTIVATE 0x30
95#define ACTIVATE_OFF 0x00
96#define ACTIVATE_ON 0x01
97
98#define BASE_ADDR_HIGH 0x60
99#define BASE_ADDR_LOW 0x61
100#define LUN_CONFIG_REG 0xF0
101#define DBASE_HIGH 0x60
102#define DBASE_LOW 0x61
103#define CBASE_HIGH 0x62
104#define CBASE_LOW 0x63
105
106
107#define LDEV_KBC1 0x00
108#define LDEV_KBC2 0x01
109#define LDEV_MOUSE 0x01
110#define LDEV_RTC_APC 0x02
111#define LDEV_FDC 0x03
112#define LDEV_PARP 0x04
113#define LDEV_UART2 0x05
114#define LDEV_UART1 0x06
115#define LDEV_GPIO 0x07
116#define LDEV_POWRMAN 0x08
117
118#define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
119#define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
120#define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
121#define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
122#define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
123#define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
124#define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
125#define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
126#define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
127#define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
128
129
130
131static inline void read_pnp_config(unsigned char index, unsigned char *data)
132{
133 pci_writeb(index,IO_INDEX);
134 pci_readb(IO_DATA, *data);
135}
136
137static inline void write_pnp_config(unsigned char index, unsigned char data)
138{
139 pci_writeb(index,IO_INDEX);
140 pci_writeb(data, IO_DATA);
141}
142
143static inline void pnp_set_device(unsigned char dev)
144{
145 write_pnp_config(LOGICAL_DEVICE, dev);
146}
147
148static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
149{
150 pci_writeb(index, CONFIG_SYS_ISA_IO + base);
151 eieio();
152 pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
153}
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158
159#define PNP_SET_DEVICE_BASE(dev,base) \
160 pnp_set_device(dev); \
161 write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
162 write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
163 write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
164 write_pnp_config(ACTIVATE, ACTIVATE_ON);
165
166#define PNP_ACTIVATE_DEVICE(dev) \
167 pnp_set_device(dev); \
168 write_pnp_config(ACTIVATE, ACTIVATE_ON);
169
170#define PNP_DEACTIVATE_DEVICE(dev) \
171 pnp_set_device(dev); \
172 write_pnp_config(ACTIVATE, ACTIVATE_OFF);
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174
175static inline void write_pgcs_config(unsigned char index, unsigned char data)
176{
177 write_pnp_config(PGCS_INDEX, index);
178 write_pnp_config(PGCS_DATA, data);
179}
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185
186
187#define PGCS_CS_ASSERT_ON_WRITE 0x10
188#define PGCS_CS_ASSERT_ON_READ 0x20
189
190#define PNP_PGCS_CSLINE_BASE(cs, base) \
191 write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
192 write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
193
194#define PNP_PGCS_CSLINE_CONF(cs, conf) \
195 write_pgcs_config(((cs) << 2) + 2, (conf) );
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201
202#define MCR_MDSL_MSK 0xe0
203#define MCR_MDSL_UART 0x00
204#define MCR_MDSL_SHRPIR 0x02
205#define MCR_MDSL_SIR 0x03
206#define MCR_MDSL_CIR 0x06
207
208#define FCR_TXFTH0 0x10
209#define FCR_TXFTH1 0x20
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211
212
213
214#ifndef CONFIG_SYS_NS87308_KBC1_BASE
215#define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
216#endif
217#ifndef CONFIG_SYS_NS87308_RTC_BASE
218#define CONFIG_SYS_NS87308_RTC_BASE 0x0070
219#endif
220#ifndef CONFIG_SYS_NS87308_FDC_BASE
221#define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
222#endif
223#ifndef CONFIG_SYS_NS87308_LPT_BASE
224#define CONFIG_SYS_NS87308_LPT_BASE 0x0278
225#endif
226#ifndef CONFIG_SYS_NS87308_UART1_BASE
227#define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
228#endif
229#ifndef CONFIG_SYS_NS87308_UART2_BASE
230#define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
231#endif
232
233#endif
234