LXR uboot/include/phy.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2011 Freescale Semiconductor, Inc.
   4 *      Andy Fleming <afleming@gmail.com>
   5 *
   6 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   7 */
   8
   9#ifndef _PHY_H
  10#define _PHY_H
  11
  12#include <dm.h>
  13#include <linux/list.h>
  14#include <linux/mii.h>
  15#include <linux/ethtool.h>
  16#include <linux/mdio.h>
  17#include <phy_interface.h>
  18
  19#define PHY_FIXED_ID            0xa5a55a5a
  20/*
  21 * There is no actual id for this.
  22 * This is just a dummy id for gmii2rgmmi converter.
  23 */
  24#define PHY_GMII2RGMII_ID       0x5a5a5a5a
  25
  26#define PHY_MAX_ADDR 32
  27
  28#define PHY_FLAG_BROKEN_RESET   (1 << 0) /* soft reset not supported */
  29
  30#define PHY_DEFAULT_FEATURES    (SUPPORTED_Autoneg | \
  31                                 SUPPORTED_TP | \
  32                                 SUPPORTED_MII)
  33
  34#define PHY_10BT_FEATURES       (SUPPORTED_10baseT_Half | \
  35                                 SUPPORTED_10baseT_Full)
  36
  37#define PHY_100BT_FEATURES      (SUPPORTED_100baseT_Half | \
  38                                 SUPPORTED_100baseT_Full)
  39
  40#define PHY_1000BT_FEATURES     (SUPPORTED_1000baseT_Half | \
  41                                 SUPPORTED_1000baseT_Full)
  42
  43#define PHY_BASIC_FEATURES      (PHY_10BT_FEATURES | \
  44                                 PHY_100BT_FEATURES | \
  45                                 PHY_DEFAULT_FEATURES)
  46
  47#define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
  48                                 PHY_1000BT_FEATURES)
  49
  50#define PHY_10G_FEATURES        (PHY_GBIT_FEATURES | \
  51                                SUPPORTED_10000baseT_Full)
  52
  53#ifndef PHY_ANEG_TIMEOUT
  54#define PHY_ANEG_TIMEOUT        4000
  55#endif
  56
  57
  58struct phy_device;
  59
  60#define MDIO_NAME_LEN 32
  61
  62struct mii_dev {
  63        struct list_head link;
  64        char name[MDIO_NAME_LEN];
  65        void *priv;
  66        int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
  67        int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
  68                        u16 val);
  69        int (*reset)(struct mii_dev *bus);
  70        struct phy_device *phymap[PHY_MAX_ADDR];
  71        u32 phy_mask;
  72};
  73
  74/* struct phy_driver: a structure which defines PHY behavior
  75 *
  76 * uid will contain a number which represents the PHY.  During
  77 * startup, the driver will poll the PHY to find out what its
  78 * UID--as defined by registers 2 and 3--is.  The 32-bit result
  79 * gotten from the PHY will be masked to
  80 * discard any bits which may change based on revision numbers
  81 * unimportant to functionality
  82 *
  83 */
  84struct phy_driver {
  85        char *name;
  86        unsigned int uid;
  87        unsigned int mask;
  88        unsigned int mmds;
  89
  90        u32 features;
  91
  92        /* Called to do any driver startup necessities */
  93        /* Will be called during phy_connect */
  94        int (*probe)(struct phy_device *phydev);
  95
  96        /* Called to configure the PHY, and modify the controller
  97         * based on the results.  Should be called after phy_connect */
  98        int (*config)(struct phy_device *phydev);
  99
 100        /* Called when starting up the controller */
 101        int (*startup)(struct phy_device *phydev);
 102
 103        /* Called when bringing down the controller */
 104        int (*shutdown)(struct phy_device *phydev);
 105
 106        int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
 107        int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
 108                        u16 val);
 109        struct list_head list;
 110};
 111
 112struct phy_device {
 113        /* Information about the PHY type */
 114        /* And management functions */
 115        struct mii_dev *bus;
 116        struct phy_driver *drv;
 117        void *priv;
 118
 119#ifdef CONFIG_DM_ETH
 120        struct udevice *dev;
 121        ofnode node;
 122#else
 123        struct eth_device *dev;
 124#endif
 125
 126        /* forced speed & duplex (no autoneg)
 127         * partner speed & duplex & pause (autoneg)
 128         */
 129        int speed;
 130        int duplex;
 131
 132        /* The most recently read link state */
 133        int link;
 134        int port;
 135        phy_interface_t interface;
 136
 137        u32 advertising;
 138        u32 supported;
 139        u32 mmds;
 140
 141        int autoneg;
 142        int addr;
 143        int pause;
 144        int asym_pause;
 145        u32 phy_id;
 146        u32 flags;
 147};
 148
 149struct fixed_link {
 150        int phy_id;
 151        int duplex;
 152        int link_speed;
 153        int pause;
 154        int asym_pause;
 155};
 156
 157static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 158{
 159        struct mii_dev *bus = phydev->bus;
 160
 161        return bus->read(bus, phydev->addr, devad, regnum);
 162}
 163
 164static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
 165                        u16 val)
 166{
 167        struct mii_dev *bus = phydev->bus;
 168
 169        return bus->write(bus, phydev->addr, devad, regnum, val);
 170}
 171
 172#ifdef CONFIG_PHYLIB_10G
 173extern struct phy_driver gen10g_driver;
 174
 175/* For now, XGMII is the only 10G interface */
 176static inline int is_10g_interface(phy_interface_t interface)
 177{
 178        return interface == PHY_INTERFACE_MODE_XGMII;
 179}
 180
 181#endif
 182
 183int phy_init(void);
 184int phy_reset(struct phy_device *phydev);
 185struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
 186                phy_interface_t interface);
 187#ifdef CONFIG_DM_ETH
 188void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
 189struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 190                                struct udevice *dev,
 191                                phy_interface_t interface);
 192static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 193{
 194        if (ofnode_valid(phydev->node))
 195                return phydev->node;
 196        else
 197                return dev_ofnode(phydev->dev);
 198}
 199#else
 200void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 201struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 202                                struct eth_device *dev,
 203                                phy_interface_t interface);
 204static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 205{
 206        return ofnode_null();
 207}
 208#endif
 209int phy_startup(struct phy_device *phydev);
 210int phy_config(struct phy_device *phydev);
 211int phy_shutdown(struct phy_device *phydev);
 212int phy_register(struct phy_driver *drv);
 213int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 214int genphy_config_aneg(struct phy_device *phydev);
 215int genphy_restart_aneg(struct phy_device *phydev);
 216int genphy_update_link(struct phy_device *phydev);
 217int genphy_parse_link(struct phy_device *phydev);
 218int genphy_config(struct phy_device *phydev);
 219int genphy_startup(struct phy_device *phydev);
 220int genphy_shutdown(struct phy_device *phydev);
 221int gen10g_config(struct phy_device *phydev);
 222int gen10g_startup(struct phy_device *phydev);
 223int gen10g_shutdown(struct phy_device *phydev);
 224int gen10g_discover_mmds(struct phy_device *phydev);
 225
 226int phy_b53_init(void);
 227int phy_mv88e61xx_init(void);
 228int phy_aquantia_init(void);
 229int phy_atheros_init(void);
 230int phy_broadcom_init(void);
 231int phy_cortina_init(void);
 232int phy_davicom_init(void);
 233int phy_et1011c_init(void);
 234int phy_lxt_init(void);
 235int phy_marvell_init(void);
 236int phy_micrel_ksz8xxx_init(void);
 237int phy_micrel_ksz90x1_init(void);
 238int phy_meson_gxl_init(void);
 239int phy_natsemi_init(void);
 240int phy_realtek_init(void);
 241int phy_smsc_init(void);
 242int phy_teranetics_init(void);
 243int phy_ti_init(void);
 244int phy_vitesse_init(void);
 245int phy_xilinx_init(void);
 246int phy_mscc_init(void);
 247int phy_fixed_init(void);
 248int phy_xilinx_gmii2rgmii_init(void);
 249
 250int board_phy_config(struct phy_device *phydev);
 251int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
 252
 253/**
 254 * phy_get_interface_by_name() - Look up a PHY interface name
 255 *
 256 * @str:        PHY interface name, e.g. "mii"
 257 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 258 */
 259int phy_get_interface_by_name(const char *str);
 260
 261/**
 262 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 263 * is RGMII (all variants)
 264 * @phydev: the phy_device struct
 265 */
 266static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 267{
 268        return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
 269                phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 270}
 271
 272/**
 273 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 274 * is SGMII (all variants)
 275 * @phydev: the phy_device struct
 276 */
 277static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 278{
 279        return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
 280                phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
 281}
 282
 283/* PHY UIDs for various PHYs that are referenced in external code */
 284#define PHY_UID_CS4340          0x13e51002
 285#define PHY_UID_CS4223          0x03e57003
 286#define PHY_UID_TN2020          0x00a19410
 287#define PHY_UID_IN112525_S03    0x02107440
 288
 289#endif
 290