LXR uboot/arch/arm/mach-keystone/include/mach/clock

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * keystone2: common pll clock definitions
   4 * (C) Copyright 2012-2014
   5 *     Texas Instruments Incorporated, <www.ti.com>
   6 */
   7
   8#ifndef _CLOCK_DEFS_H_
   9#define _CLOCK_DEFS_H_
  10
  11#include <asm/arch/hardware.h>
  12
  13/* PLL Control Registers */
  14struct pllctl_regs {
  15        u32     ctl;            /* 00 */
  16        u32     ocsel;          /* 04 */
  17        u32     secctl;         /* 08 */
  18        u32     resv0;
  19        u32     mult;           /* 10 */
  20        u32     prediv;         /* 14 */
  21        u32     div1;           /* 18 */
  22        u32     div2;           /* 1c */
  23        u32     div3;           /* 20 */
  24        u32     oscdiv1;        /* 24 */
  25        u32     resv1;          /* 28 */
  26        u32     bpdiv;          /* 2c */
  27        u32     wakeup;         /* 30 */
  28        u32     resv2;
  29        u32     cmd;            /* 38 */
  30        u32     stat;           /* 3c */
  31        u32     alnctl;         /* 40 */
  32        u32     dchange;        /* 44 */
  33        u32     cken;           /* 48 */
  34        u32     ckstat;         /* 4c */
  35        u32     systat;         /* 50 */
  36        u32     ckctl;          /* 54 */
  37        u32     resv3[2];
  38        u32     div4;           /* 60 */
  39        u32     div5;           /* 64 */
  40        u32     div6;           /* 68 */
  41        u32     div7;           /* 6c */
  42        u32     div8;           /* 70 */
  43        u32     div9;           /* 74 */
  44        u32     div10;          /* 78 */
  45        u32     div11;          /* 7c */
  46        u32     div12;          /* 80 */
  47};
  48
  49static struct pllctl_regs *pllctl_regs[] = {
  50        (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
  51};
  52
  53#define pllctl_reg(pll, reg)            (&(pllctl_regs[pll]->reg))
  54#define pllctl_reg_read(pll, reg)       __raw_readl(pllctl_reg(pll, reg))
  55#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
  56
  57#define pllctl_reg_rmw(pll, reg, mask, val) \
  58        pllctl_reg_write(pll, reg, \
  59                (pllctl_reg_read(pll, reg) & ~(mask)) | val)
  60
  61#define pllctl_reg_setbits(pll, reg, mask) \
  62        pllctl_reg_rmw(pll, reg, 0, mask)
  63
  64#define pllctl_reg_clrbits(pll, reg, mask) \
  65        pllctl_reg_rmw(pll, reg, mask, 0)
  66
  67#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
  68
  69/* PLLCTL Bits */
  70#define PLLCTL_PLLENSRC_SHIF    5
  71#define PLLCTL_PLLENSRC_MASK    BIT(5)
  72#define PLLCTL_PLLRST_SHIFT     3
  73#define PLLCTL_PLLRST_MASK      BIT(3)
  74#define PLLCTL_PLLPWRDN_SHIFT   1
  75#define PLLCTL_PLLPWRDN_MASK    BIT(1)
  76#define PLLCTL_PLLEN_SHIFT      0
  77#define PLLCTL_PLLEN_MASK       BIT(0)
  78
  79/* SECCTL Bits */
  80#define SECCTL_BYPASS_SHIFT     23
  81#define SECCTL_BYPASS_MASK      BIT(23)
  82#define SECCTL_OP_DIV_SHIFT     19
  83#define SECCTL_OP_DIV_MASK      (0xf << 19)
  84
  85/* PLLM Bits */
  86#define PLLM_MULT_LO_SHIFT      0
  87#define PLLM_MULT_LO_MASK       0x3f
  88#define PLLM_MULT_LO_BITS       6
  89
  90/* PLLDIVn Bits */
  91#define PLLDIV_ENABLE_SHIFT     15
  92#define PLLDIV_ENABLE_MASK      BIT(15)
  93#define PLLDIV_RATIO_SHIFT      0x0
  94#define PLLDIV_RATIO_MASK       0xff
  95#define PLLDIV_MAX              16
  96
  97/* PLLCMD Bits */
  98#define PLLCMD_GOSET_SHIFT      0
  99#define PLLCMD_GOSET_MASK       BIT(0)
 100
 101/* PLLSTAT Bits */
 102#define PLLSTAT_GOSTAT_SHIFT    0
 103#define PLLSTAT_GOSTAT_MASK     BIT(0)
 104
 105/* Device Config PLLCTL0 */
 106#define CFG_PLLCTL0_BWADJ_SHIFT         24
 107#define CFG_PLLCTL0_BWADJ_MASK          (0xff << 24)
 108#define CFG_PLLCTL0_BWADJ_BITS          8
 109#define CFG_PLLCTL0_BYPASS_SHIFT        23
 110#define CFG_PLLCTL0_BYPASS_MASK         BIT(23)
 111#define CFG_PLLCTL0_CLKOD_SHIFT         19
 112#define CFG_PLLCTL0_CLKOD_MASK          (0xf << 19)
 113#define CFG_PLLCTL0_PLLM_HI_SHIFT       12
 114#define CFG_PLLCTL0_PLLM_HI_MASK        (0x7f << 12)
 115#define CFG_PLLCTL0_PLLM_SHIFT          6
 116#define CFG_PLLCTL0_PLLM_MASK           (0x1fff << 6)
 117#define CFG_PLLCTL0_PLLD_SHIFT          0
 118#define CFG_PLLCTL0_PLLD_MASK           0x3f
 119
 120/* Device Config PLLCTL1 */
 121#define CFG_PLLCTL1_RST_SHIFT   14
 122#define CFG_PLLCTL1_RST_MASK    BIT(14)
 123#define CFG_PLLCTL1_PAPLL_SHIFT 13
 124#define CFG_PLLCTL1_PAPLL_MASK  BIT(13)
 125#define CFG_PLLCTL1_ENSAT_SHIFT 6
 126#define CFG_PLLCTL1_ENSAT_MASK  BIT(6)
 127#define CFG_PLLCTL1_BWADJ_SHIFT 0
 128#define CFG_PLLCTL1_BWADJ_MASK  0xf
 129
 130#define MISC_CTL1_ARM_PLL_EN    BIT(13)
 131
 132#endif  /* _CLOCK_DEFS_H_ */
 133