LXR uboot/arch/mips/mach-mscc/dram.c

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2018 Microsemi Corporation
   4 */
   5
   6#include <common.h>
   7
   8#include <asm/io.h>
   9#include <asm/types.h>
  10
  11#include <mach/tlb.h>
  12#include <mach/ddr.h>
  13
  14DECLARE_GLOBAL_DATA_PTR;
  15
  16static inline int vcoreiii_train_bytelane(void)
  17{
  18        int ret;
  19
  20        ret = hal_vcoreiii_train_bytelane(0);
  21
  22#ifdef CONFIG_SOC_OCELOT
  23        if (ret)
  24                return ret;
  25        ret = hal_vcoreiii_train_bytelane(1);
  26#endif
  27
  28        return ret;
  29}
  30
  31int vcoreiii_ddr_init(void)
  32{
  33        int res;
  34
  35        if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
  36              & ICPU_MEMCTRL_STAT_INIT_DONE)) {
  37                hal_vcoreiii_init_memctl();
  38                hal_vcoreiii_wait_memctl();
  39                if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
  40                        hal_vcoreiii_ddr_failed();
  41        }
  42#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
  43        res = dram_check();
  44        if (res == 0)
  45                hal_vcoreiii_ddr_verified();
  46        else
  47                hal_vcoreiii_ddr_failed();
  48
  49        /* Clear boot-mode and read-back to activate/verify */
  50        clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  51                     ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
  52        readl(BASE_CFG + ICPU_GENERAL_CTRL);
  53#else
  54        res = 0;
  55#endif
  56        return res;
  57}
  58
  59int print_cpuinfo(void)
  60{
  61        printf("MSCC VCore-III MIPS 24Kec\n");
  62
  63        return 0;
  64}
  65
  66int dram_init(void)
  67{
  68        while (vcoreiii_ddr_init())
  69                ;
  70
  71        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  72        return 0;
  73}
  74