LXR uboot/arch/x86/cpu/intel_common/report

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
   4 *
   5 * Copyright (C) 2012 Google Inc.
   6 */
   7
   8#include <common.h>
   9#include <asm/cpu.h>
  10#include <asm/pci.h>
  11#include <asm/report_platform.h>
  12#include <asm/arch/pch.h>
  13
  14static void report_cpu_info(void)
  15{
  16        char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
  17        const char *mode[] = {"NOT ", ""};
  18        struct cpuid_result cpuidr;
  19        int vt, txt, aes;
  20        u32 index;
  21
  22        index = 0x80000000;
  23        cpuidr = cpuid(index);
  24        if (cpuidr.eax < 0x80000004) {
  25                strcpy(cpu_string, "Platform info not available");
  26                cpu_name = cpu_string;
  27        } else {
  28                cpu_name = cpu_get_name(cpu_string);
  29        }
  30
  31        cpuidr = cpuid(1);
  32        debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
  33        aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
  34        txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
  35        vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
  36        debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
  37              mode[aes], mode[txt], mode[vt]);
  38}
  39
  40/* The PCI id name match comes from Intel document 472178 */
  41static struct {
  42        u16 dev_id;
  43        const char *dev_name;
  44} pch_table[] = {
  45        {0x1E41, "Desktop Sample"},
  46        {0x1E42, "Mobile Sample"},
  47        {0x1E43, "SFF Sample"},
  48        {0x1E44, "Z77"},
  49        {0x1E45, "H71"},
  50        {0x1E46, "Z75"},
  51        {0x1E47, "Q77"},
  52        {0x1E48, "Q75"},
  53        {0x1E49, "B75"},
  54        {0x1E4A, "H77"},
  55        {0x1E53, "C216"},
  56        {0x1E55, "QM77"},
  57        {0x1E56, "QS77"},
  58        {0x1E58, "UM77"},
  59        {0x1E57, "HM77"},
  60        {0x1E59, "HM76"},
  61        {0x1E5D, "HM75"},
  62        {0x1E5E, "HM70"},
  63        {0x1E5F, "NM70"},
  64};
  65
  66static void report_pch_info(struct udevice *dev)
  67{
  68        const char *pch_type = "Unknown";
  69        int i;
  70        u16 dev_id;
  71        uint8_t rev_id;
  72
  73        dm_pci_read_config16(dev, 2, &dev_id);
  74        for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
  75                if (pch_table[i].dev_id == dev_id) {
  76                        pch_type = pch_table[i].dev_name;
  77                        break;
  78                }
  79        }
  80        dm_pci_read_config8(dev, 8, &rev_id);
  81        debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
  82              rev_id);
  83}
  84
  85void report_platform_info(struct udevice *dev)
  86{
  87        report_cpu_info();
  88        report_pch_info(dev);
  89}
  90