uboot/board/BuS/eb_cpu5282/eb_cpu5282.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2005-2009
   4 * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   5 *
   6 * (C) Copyright 2000-2003
   7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8 */
   9
  10#include <common.h>
  11#include <command.h>
  12#include "asm/m5282.h"
  13#include <bmp_layout.h>
  14#include <status_led.h>
  15#include <bus_vcxk.h>
  16
  17/*---------------------------------------------------------------------------*/
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21#ifdef CONFIG_VIDEO
  22unsigned long display_width;
  23unsigned long display_height;
  24#endif
  25
  26/*---------------------------------------------------------------------------*/
  27
  28int checkboard (void)
  29{
  30        puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
  31#if (CONFIG_SYS_TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
  32        puts("       Boot from Internal FLASH\n");
  33#endif
  34        return 0;
  35}
  36
  37int dram_init(void)
  38{
  39        int size, i;
  40
  41        size = 0;
  42        MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
  43                        MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
  44        asm (" nop");
  45#ifdef CONFIG_SYS_SDRAM_BASE0
  46        MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
  47                MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
  48                MCFSDRAMC_DACR_PS_32;
  49        asm (" nop");
  50
  51        MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
  52        asm (" nop");
  53
  54        MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
  55        asm (" nop");
  56        for (i = 0; i < 10; i++)
  57                asm (" nop");
  58
  59        *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
  60        asm (" nop");
  61        MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
  62        asm (" nop");
  63
  64        for (i = 0; i < 2000; i++)
  65                asm (" nop");
  66
  67        MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
  68        asm (" nop");
  69        /* write SDRAM mode register */
  70        *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
  71        asm (" nop");
  72        size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
  73#endif
  74#ifdef CONFIG_SYS_SDRAM_BASE1xx
  75        MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
  76                        | MCFSDRAMC_DACR_CASL (1)
  77                        | MCFSDRAMC_DACR_CBM (3)
  78                        | MCFSDRAMC_DACR_PS_16;
  79
  80        MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
  81
  82        MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
  83
  84        *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
  85        MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
  86
  87        for (i = 0; i < 2000; i++)
  88                asm (" nop");
  89
  90        MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
  91        *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
  92        size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
  93#endif
  94        gd->ram_size = size;
  95
  96        return 0;
  97}
  98
  99#if defined(CONFIG_SYS_DRAM_TEST)
 100int testdram (void)
 101{
 102        uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 103        uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 104        uint *p;
 105
 106        printf("SDRAM test phase 1:\n");
 107        for (p = pstart; p < pend; p++)
 108                *p = 0xaaaaaaaa;
 109
 110        for (p = pstart; p < pend; p++) {
 111                if (*p != 0xaaaaaaaa) {
 112                        printf ("SDRAM test fails at: %08x\n", (uint) p);
 113                        return 1;
 114                }
 115        }
 116
 117        printf("SDRAM test phase 2:\n");
 118        for (p = pstart; p < pend; p++)
 119                *p = 0x55555555;
 120
 121        for (p = pstart; p < pend; p++) {
 122                if (*p != 0x55555555) {
 123                        printf ("SDRAM test fails at: %08x\n", (uint) p);
 124                        return 1;
 125                }
 126        }
 127
 128        printf("SDRAM test passed.\n");
 129        return 0;
 130}
 131#endif
 132
 133#if defined(CONFIG_HW_WATCHDOG)
 134
 135void hw_watchdog_init(void)
 136{
 137        char *s;
 138        int enable;
 139
 140        enable = 1;
 141        s = env_get("watchdog");
 142        if (s != NULL)
 143                if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0))
 144                        enable = 0;
 145        if (enable)
 146                MCFGPTA_GPTDDR  |= (1<<2);
 147        else
 148                MCFGPTA_GPTDDR  &= ~(1<<2);
 149}
 150
 151void hw_watchdog_reset(void)
 152{
 153        MCFGPTA_GPTPORT  ^= (1<<2);
 154}
 155#endif
 156
 157int misc_init_r(void)
 158{
 159#ifdef  CONFIG_HW_WATCHDOG
 160        hw_watchdog_init();
 161#endif
 162        return 1;
 163}
 164
 165void __led_toggle(led_id_t mask)
 166{
 167        MCFGPTA_GPTPORT ^= (1 << 3);
 168}
 169
 170void __led_init(led_id_t mask, int state)
 171{
 172        __led_set(mask, state);
 173        MCFGPTA_GPTDDR  |= (1 << 3);
 174}
 175
 176void __led_set(led_id_t mask, int state)
 177{
 178        if (state == CONFIG_LED_STATUS_ON)
 179                MCFGPTA_GPTPORT |= (1 << 3);
 180        else
 181                MCFGPTA_GPTPORT &= ~(1 << 3);
 182}
 183
 184#if defined(CONFIG_VIDEO)
 185
 186int drv_video_init(void)
 187{
 188        char *s;
 189#ifdef CONFIG_SPLASH_SCREEN
 190        unsigned long splash;
 191#endif
 192        printf("Init Video as ");
 193        s = env_get("displaywidth");
 194        if (s != NULL)
 195                display_width = simple_strtoul(s, NULL, 10);
 196        else
 197                display_width = 256;
 198
 199        s = env_get("displayheight");
 200        if (s != NULL)
 201                display_height = simple_strtoul(s, NULL, 10);
 202        else
 203                display_height = 256;
 204
 205        printf("%lu x %lu pixel matrix\n", display_width, display_height);
 206
 207        MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
 208        MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
 209
 210        vcxk_init(display_width, display_height);
 211
 212#ifdef CONFIG_SPLASH_SCREEN
 213        s = env_get("splashimage");
 214        if (s != NULL) {
 215                splash = simple_strtoul(s, NULL, 16);
 216                vcxk_acknowledge_wait();
 217                video_display_bitmap(splash, 0, 0);
 218        }
 219#endif
 220        return 0;
 221}
 222#endif
 223
 224/*---------------------------------------------------------------------------*/
 225
 226#ifdef CONFIG_VIDEO
 227int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 228{
 229        int rcode = 0;
 230        ulong side;
 231        ulong bright;
 232
 233        switch (argc) {
 234        case 3:
 235                side = simple_strtoul(argv[1], NULL, 10);
 236                bright = simple_strtoul(argv[2], NULL, 10);
 237                if ((side >= 0) && (side <= 3) &&
 238                        (bright >= 0) && (bright <= 1000)) {
 239                        vcxk_setbrightness(side, bright);
 240                        rcode = 0;
 241                } else {
 242                        printf("parameters out of range\n");
 243                        printf("Usage:\n%s\n", cmdtp->usage);
 244                        rcode = 1;
 245                }
 246                break;
 247        default:
 248                printf("Usage:\n%s\n", cmdtp->usage);
 249                rcode = 1;
 250                break;
 251        }
 252        return rcode;
 253}
 254
 255/*---------------------------------------------------------------------------*/
 256
 257U_BOOT_CMD(
 258        bright, 3,      0,      do_brightness,
 259        "sets the display brightness\n",
 260        " <side> <0..1000>\n        side: 0/3=both; 1=first; 2=second\n"
 261);
 262
 263#endif
 264
 265/* EOF EB+MCF-EV123.c */
 266