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7#include <common.h>
8#include <hwconfig.h>
9#include <i2c.h>
10#include <spi.h>
11#include <linux/libfdt.h>
12#include <fdt_support.h>
13#include <pci.h>
14#include <mpc83xx.h>
15#include <fsl_esdhc.h>
16#include <asm/io.h>
17#include <asm/fsl_serdes.h>
18#include <asm/fsl_mpc83xx_serdes.h>
19
20#include "mpc8308.h"
21
22#include <gdsys_fpga.h>
23
24#include "../common/ioep-fpga.h"
25#include "../common/osd.h"
26#include "../common/mclink.h"
27#include "../common/phy.h"
28#include "../common/fanctrl.h"
29
30#include <pca953x.h>
31#include <pca9698.h>
32
33#include <miiphy.h>
34
35#define MAX_MUX_CHANNELS 2
36
37enum {
38 MCFPGA_DONE = 1 << 0,
39 MCFPGA_INIT_N = 1 << 1,
40 MCFPGA_PROGRAM_N = 1 << 2,
41 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
42 MCFPGA_RESET_N = 1 << 4,
43};
44
45enum {
46 GPIO_MDC = 1 << 14,
47 GPIO_MDIO = 1 << 15,
48};
49
50unsigned int mclink_fpgacount;
51struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
52
53struct {
54 u8 bus;
55 u8 addr;
56} hrcon_fans[] = CONFIG_HRCON_FANS;
57
58int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
59{
60 int res;
61
62 switch (fpga) {
63 case 0:
64 out_le16(reg, data);
65 break;
66 default:
67 res = mclink_send(fpga - 1, regoff, data);
68 if (res < 0) {
69 printf("mclink_send reg %02lx data %04x returned %d\n",
70 regoff, data, res);
71 return res;
72 }
73 break;
74 }
75
76 return 0;
77}
78
79int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
80{
81 int res;
82
83 switch (fpga) {
84 case 0:
85 *data = in_le16(reg);
86 break;
87 default:
88 if (fpga > mclink_fpgacount)
89 return -EINVAL;
90 res = mclink_receive(fpga - 1, regoff, data);
91 if (res < 0) {
92 printf("mclink_receive reg %02lx returned %d\n",
93 regoff, res);
94 return res;
95 }
96 }
97
98 return 0;
99}
100
101int checkboard(void)
102{
103 char *s = env_get("serial#");
104 bool hw_type_cat = pca9698_get_value(0x20, 20);
105
106 puts("Board: ");
107
108 printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
109
110 if (s != NULL) {
111 puts(", serial# ");
112 puts(s);
113 }
114
115 puts("\n");
116
117 return 0;
118}
119
120int last_stage_init(void)
121{
122 int slaves;
123 unsigned int k;
124 unsigned int mux_ch;
125 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
126 u16 fpga_features;
127 bool hw_type_cat = pca9698_get_value(0x20, 20);
128 bool ch0_rgmii2_present = false;
129
130 FPGA_GET_REG(0, fpga_features, &fpga_features);
131
132
133 pca9698_direction_output(0x20, 10, 1);
134 pca9698_direction_output(0x20, 11, 1);
135
136 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
137
138
139 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
140 unsigned int ctr = 0;
141
142 if (i2c_probe(mclink_controllers[k]))
143 continue;
144
145 while (!(pca953x_get_val(mclink_controllers[k])
146 & MCFPGA_DONE)) {
147 udelay(100000);
148 if (ctr++ > 5) {
149 printf("no done for mclink_controller %d\n", k);
150 break;
151 }
152 }
153
154 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
155 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
156 udelay(10);
157 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
158 MCFPGA_RESET_N);
159 }
160
161 if (hw_type_cat) {
162 int retval;
163 struct mii_dev *mdiodev = mdio_alloc();
164 if (!mdiodev)
165 return -ENOMEM;
166 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
167 mdiodev->read = bb_miiphy_read;
168 mdiodev->write = bb_miiphy_write;
169
170 retval = mdio_register(mdiodev);
171 if (retval < 0)
172 return retval;
173 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
174 if ((mux_ch == 1) && !ch0_rgmii2_present)
175 continue;
176
177 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
178 }
179 }
180
181
182 udelay(500000);
183
184 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
185 slaves = mclink_probe();
186 mclink_fpgacount = 0;
187
188 ioep_fpga_print_info(0);
189 osd_probe(0);
190#ifdef CONFIG_SYS_OSD_DH
191 osd_probe(4);
192#endif
193
194 if (slaves <= 0)
195 return 0;
196
197 mclink_fpgacount = slaves;
198
199 for (k = 1; k <= slaves; ++k) {
200 FPGA_GET_REG(k, fpga_features, &fpga_features);
201
202 ioep_fpga_print_info(k);
203 osd_probe(k);
204#ifdef CONFIG_SYS_OSD_DH
205 osd_probe(k + 4);
206#endif
207 if (hw_type_cat) {
208 int retval;
209 struct mii_dev *mdiodev = mdio_alloc();
210 if (!mdiodev)
211 return -ENOMEM;
212 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
213 MDIO_NAME_LEN);
214 mdiodev->read = bb_miiphy_read;
215 mdiodev->write = bb_miiphy_write;
216
217 retval = mdio_register(mdiodev);
218 if (retval < 0)
219 return retval;
220 setup_88e1514(bb_miiphy_buses[k].name, 0);
221 }
222 }
223
224 for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
225 i2c_set_bus_num(hrcon_fans[k].bus);
226 init_fan_controller(hrcon_fans[k].addr);
227 }
228
229 return 0;
230}
231
232
233
234
235
236void fpga_gpio_set(unsigned int bus, int pin)
237{
238 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
239}
240
241void fpga_gpio_clear(unsigned int bus, int pin)
242{
243 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
244}
245
246int fpga_gpio_get(unsigned int bus, int pin)
247{
248 u16 val;
249
250 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
251
252 return val & pin;
253}
254
255void fpga_control_set(unsigned int bus, int pin)
256{
257 u16 val;
258
259 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
260 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
261}
262
263void fpga_control_clear(unsigned int bus, int pin)
264{
265 u16 val;
266
267 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
268 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
269}
270
271void mpc8308_init(void)
272{
273 pca9698_direction_output(0x20, 4, 1);
274}
275
276void mpc8308_set_fpga_reset(unsigned state)
277{
278 pca9698_set_value(0x20, 4, state ? 0 : 1);
279}
280
281void mpc8308_setup_hw(void)
282{
283 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
284
285
286
287
288 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
289 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
290}
291
292int mpc8308_get_fpga_done(unsigned fpga)
293{
294 return pca9698_get_value(0x20, 19);
295}
296
297#ifdef CONFIG_FSL_ESDHC
298int board_mmc_init(bd_t *bd)
299{
300 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
301 sysconf83xx_t *sysconf = &immr->sysconf;
302
303
304 out_be32(&sysconf->sdhccr, 0x02000000);
305
306 return fsl_esdhc_mmc_init(bd);
307}
308#endif
309
310static struct pci_region pcie_regions_0[] = {
311 {
312 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
313 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
314 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
315 .flags = PCI_REGION_MEM,
316 },
317 {
318 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
319 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
320 .size = CONFIG_SYS_PCIE1_IO_SIZE,
321 .flags = PCI_REGION_IO,
322 },
323};
324
325void pci_init_board(void)
326{
327 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
328 sysconf83xx_t *sysconf = &immr->sysconf;
329 law83xx_t *pcie_law = sysconf->pcielaw;
330 struct pci_region *pcie_reg[] = { pcie_regions_0 };
331
332 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
333 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
334
335
336 out_be32(&sysconf->pecr1, 0xE0008000);
337 udelay(2000);
338
339
340 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
341 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
342
343 mpc83xx_pcie_init(1, pcie_reg);
344}
345
346ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
347{
348 info->portwidth = FLASH_CFI_16BIT;
349 info->chipwidth = FLASH_CFI_BY16;
350 info->interface = FLASH_CFI_X16;
351 return 1;
352}
353
354#if defined(CONFIG_OF_BOARD_SETUP)
355int ft_board_setup(void *blob, bd_t *bd)
356{
357 ft_cpu_setup(blob, bd);
358 fsl_fdt_fixup_dr_usb(blob, bd);
359 fdt_fixup_esdhc(blob, bd);
360
361 return 0;
362}
363#endif
364
365
366
367
368
369struct fpga_mii {
370 unsigned fpga;
371 int mdio;
372} fpga_mii[] = {
373 { 0, 1},
374 { 1, 1},
375 { 2, 1},
376 { 3, 1},
377};
378
379static int mii_dummy_init(struct bb_miiphy_bus *bus)
380{
381 return 0;
382}
383
384static int mii_mdio_active(struct bb_miiphy_bus *bus)
385{
386 struct fpga_mii *fpga_mii = bus->priv;
387
388 if (fpga_mii->mdio)
389 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
390 else
391 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
392
393 return 0;
394}
395
396static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
397{
398 struct fpga_mii *fpga_mii = bus->priv;
399
400 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
401
402 return 0;
403}
404
405static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
406{
407 struct fpga_mii *fpga_mii = bus->priv;
408
409 if (v)
410 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
411 else
412 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
413
414 fpga_mii->mdio = v;
415
416 return 0;
417}
418
419static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
420{
421 u16 gpio;
422 struct fpga_mii *fpga_mii = bus->priv;
423
424 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
425
426 *v = ((gpio & GPIO_MDIO) != 0);
427
428 return 0;
429}
430
431static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
432{
433 struct fpga_mii *fpga_mii = bus->priv;
434
435 if (v)
436 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
437 else
438 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
439
440 return 0;
441}
442
443static int mii_delay(struct bb_miiphy_bus *bus)
444{
445 udelay(1);
446
447 return 0;
448}
449
450struct bb_miiphy_bus bb_miiphy_buses[] = {
451 {
452 .name = "board0",
453 .init = mii_dummy_init,
454 .mdio_active = mii_mdio_active,
455 .mdio_tristate = mii_mdio_tristate,
456 .set_mdio = mii_set_mdio,
457 .get_mdio = mii_get_mdio,
458 .set_mdc = mii_set_mdc,
459 .delay = mii_delay,
460 .priv = &fpga_mii[0],
461 },
462 {
463 .name = "board1",
464 .init = mii_dummy_init,
465 .mdio_active = mii_mdio_active,
466 .mdio_tristate = mii_mdio_tristate,
467 .set_mdio = mii_set_mdio,
468 .get_mdio = mii_get_mdio,
469 .set_mdc = mii_set_mdc,
470 .delay = mii_delay,
471 .priv = &fpga_mii[1],
472 },
473 {
474 .name = "board2",
475 .init = mii_dummy_init,
476 .mdio_active = mii_mdio_active,
477 .mdio_tristate = mii_mdio_tristate,
478 .set_mdio = mii_set_mdio,
479 .get_mdio = mii_get_mdio,
480 .set_mdc = mii_set_mdc,
481 .delay = mii_delay,
482 .priv = &fpga_mii[2],
483 },
484 {
485 .name = "board3",
486 .init = mii_dummy_init,
487 .mdio_active = mii_mdio_active,
488 .mdio_tristate = mii_mdio_tristate,
489 .set_mdio = mii_set_mdio,
490 .get_mdio = mii_get_mdio,
491 .set_mdc = mii_set_mdc,
492 .delay = mii_delay,
493 .priv = &fpga_mii[3],
494 },
495};
496
497int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
498 sizeof(bb_miiphy_buses[0]);
499
