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8#include <common.h>
9#include <malloc.h>
10#include <dm/platform_data/serial_sh.h>
11#include <asm/processor.h>
12#include <asm/mach-types.h>
13#include <asm/io.h>
14#include <linux/errno.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
17#include <asm/arch/rmobile.h>
18#include <asm/arch/rcar-mstp.h>
19
20#include <spl.h>
21
22#define TMU0_MSTP125 BIT(25)
23#define SCIF0_MSTP721 BIT(21)
24#define QSPI_MSTP917 BIT(17)
25
26#define SD2CKCR 0xE615026C
27#define SD_97500KHZ 0x7
28
29struct reg_config {
30 u16 off;
31 u32 val;
32};
33
34static void dbsc_wait(u16 reg)
35{
36 static const u32 dbsc3_0_base = DBSC3_0_BASE;
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
38
39 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
40 ;
41
42 while (!(readl(dbsc3_1_base + reg) & BIT(0)))
43 ;
44}
45
46static void spl_init_sys(void)
47{
48 u32 r0 = 0;
49
50 writel(0xa5a5a500, 0xe6020004);
51 writel(0xa5a5a500, 0xe6030004);
52
53 asm volatile(
54
55 "mcr 15, 0, %0, cr7, cr5, 0 \n"
56
57 "mcr 15, 0, %0, cr7, cr5, 6 \n"
58
59 "mrc 15, 0, %0, cr1, cr0, 0 \n"
60 "orr %0, #0x1800 \n"
61 "mcr 15, 0, %0, cr1, cr0, 0 \n"
62 "isb sy \n"
63 :"=r"(r0));
64}
65
66static void spl_init_pfc(void)
67{
68 static const struct reg_config pfc_with_unlock[] = {
69 { 0x0090, 0x60000000 },
70 { 0x0094, 0x60000000 },
71 { 0x0098, 0x00800200 },
72 { 0x009c, 0x00000000 },
73 { 0x0020, 0x00000000 },
74 { 0x0024, 0x00000000 },
75 { 0x0028, 0x000244c8 },
76 { 0x002c, 0x00000000 },
77 { 0x0030, 0x00002400 },
78 { 0x0034, 0x01520000 },
79 { 0x0038, 0x00724003 },
80 { 0x003c, 0x00000000 },
81 { 0x0040, 0x00000000 },
82 { 0x0044, 0x00000000 },
83 { 0x0048, 0x00000000 },
84 { 0x004c, 0x00000000 },
85 { 0x0050, 0x00000000 },
86 { 0x0054, 0x00000000 },
87 { 0x0058, 0x00000000 },
88 { 0x005c, 0x00000000 },
89 { 0x0160, 0x00000000 },
90 { 0x0004, 0xffffffff },
91 { 0x0008, 0x00ec3fff },
92 { 0x000c, 0x3bc001e7 },
93 { 0x0010, 0x5bffffff },
94 { 0x0014, 0x1ffffffb },
95 { 0x0018, 0x01bffff0 },
96 { 0x001c, 0xcf7fffff },
97 { 0x0074, 0x0381fc00 },
98 };
99
100 static const struct reg_config pfc_without_unlock[] = {
101 { 0x0100, 0xffffffdf },
102 { 0x0104, 0xc883c3ff },
103 { 0x0108, 0x1201f3c9 },
104 { 0x010c, 0x00000000 },
105 { 0x0110, 0xffffeb04 },
106 { 0x0114, 0xc003ffff },
107 { 0x0118, 0x0800000f },
108 { 0x011c, 0x00187ff0 },
109 };
110
111 static const u32 pfc_base = 0xe6060000;
112
113 unsigned int i;
114
115 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
116 writel(~pfc_with_unlock[i].val, pfc_base);
117 writel(pfc_with_unlock[i].val,
118 pfc_base | pfc_with_unlock[i].off);
119 }
120
121 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
122 writel(pfc_without_unlock[i].val,
123 pfc_base | pfc_without_unlock[i].off);
124}
125
126static void spl_init_gpio(void)
127{
128 static const u16 gpio_offs[] = {
129 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
130 };
131
132 static const struct reg_config gpio_set[] = {
133 { 0x2000, 0x04381000 },
134 { 0x5000, 0x00000000 },
135 { 0x5800, 0x000e0000 },
136 };
137
138 static const struct reg_config gpio_clr[] = {
139 { 0x1000, 0x00000000 },
140 { 0x2000, 0x04381010 },
141 { 0x3000, 0x00000000 },
142 { 0x4000, 0x00000000 },
143 { 0x5000, 0x00400000 },
144 { 0x5400, 0x00000000 },
145 { 0x5800, 0x000e0380 },
146 };
147
148 static const u32 gpio_base = 0xe6050000;
149
150 unsigned int i;
151
152 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
153 writel(0, gpio_base | 0x20 | gpio_offs[i]);
154
155 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
156 writel(0, gpio_base | 0x00 | gpio_offs[i]);
157
158 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
159 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
160
161 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
162 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
163}
164
165static void spl_init_lbsc(void)
166{
167 static const struct reg_config lbsc_config[] = {
168 { 0x00, 0x00000020 },
169 { 0x08, 0x00002020 },
170 { 0x30, 0x2a103320 },
171 { 0x38, 0xff70ff70 },
172 };
173
174 static const u16 lbsc_offs[] = {
175 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
176 };
177
178 static const u32 lbsc_base = 0xfec00200;
179
180 unsigned int i;
181
182 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
183 writel(lbsc_config[i].val,
184 lbsc_base | lbsc_config[i].off);
185 writel(lbsc_config[i].val,
186 lbsc_base | (lbsc_config[i].off + 4));
187 }
188
189 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
190 writel(0, lbsc_base | lbsc_offs[i]);
191}
192
193static void spl_init_dbsc(void)
194{
195 static const struct reg_config dbsc_config1[] = {
196 { 0x0280, 0x0000a55a },
197 { 0x4000, 0x0000a55a },
198 { 0x4008, 0x00000001 },
199 { 0x0018, 0x21000000 },
200 { 0x0018, 0x11000000 },
201 { 0x0018, 0x10000000 },
202 { 0x0290, 0x00000001 },
203 { 0x02a0, 0x80000000 },
204 { 0x0290, 0x00000004 },
205 };
206
207 static const struct reg_config dbsc_config2[] = {
208 { 0x0290, 0x00000006 },
209 { 0x02a0, 0x0001c000 },
210 };
211
212 static const struct reg_config dbsc_config3r0d0[] = {
213 { 0x0290, 0x0000000f },
214 { 0x02a0, 0x00181885 },
215 { 0x0290, 0x00000070 },
216 { 0x02a0, 0x7c000887 },
217 { 0x0290, 0x00000080 },
218 { 0x02a0, 0x7c000887 },
219 { 0x0290, 0x00000090 },
220 { 0x02a0, 0x7c000887 },
221 { 0x0290, 0x000000a0 },
222 { 0x02a0, 0x7c000887 },
223 { 0x0290, 0x000000b0 },
224 { 0x02a0, 0x7c000880 },
225 { 0x0290, 0x000000c0 },
226 { 0x02a0, 0x7c000880 },
227 { 0x0290, 0x000000d0 },
228 { 0x02a0, 0x7c000880 },
229 { 0x0290, 0x000000e0 },
230 { 0x02a0, 0x7c000880 },
231 };
232 static const struct reg_config dbsc_config3r0d1[] = {
233 { 0x0290, 0x0000000f },
234 { 0x02a0, 0x00181885 },
235 { 0x0290, 0x00000070 },
236 { 0x02a0, 0x7c000887 },
237 { 0x0290, 0x00000080 },
238 { 0x02a0, 0x7c000887 },
239 { 0x0290, 0x00000090 },
240 { 0x02a0, 0x7c000887 },
241 { 0x0290, 0x000000a0 },
242 { 0x02a0, 0x7c000887 },
243 };
244
245 static const struct reg_config dbsc_config3r2[] = {
246 { 0x0290, 0x0000000f },
247 { 0x02a0, 0x00181224 },
248 };
249
250 static const struct reg_config dbsc_config4[] = {
251 { 0x0290, 0x00000010 },
252 { 0x02a0, 0xf004649b },
253 { 0x0290, 0x00000061 },
254 { 0x02a0, 0x0000006d },
255 { 0x0290, 0x00000001 },
256 { 0x02a0, 0x00000073 },
257 { 0x0020, 0x00000007 },
258 { 0x0024, 0x0f030a02 },
259 { 0x0030, 0x00000001 },
260 { 0x00b0, 0x00000000 },
261 { 0x0040, 0x0000000b },
262 { 0x0044, 0x00000008 },
263 { 0x0048, 0x00000000 },
264 { 0x0050, 0x0000000b },
265 { 0x0054, 0x000c000b },
266 { 0x0058, 0x00000027 },
267 { 0x005c, 0x0000001c },
268 { 0x0060, 0x00000006 },
269 { 0x0064, 0x00000020 },
270 { 0x0068, 0x00000008 },
271 { 0x006c, 0x0000000c },
272 { 0x0070, 0x00000009 },
273 { 0x0074, 0x00000012 },
274 { 0x0078, 0x000000d0 },
275 { 0x007c, 0x00140005 },
276 { 0x0080, 0x00050004 },
277 { 0x0084, 0x70233005 },
278 { 0x0088, 0x000c0000 },
279 { 0x008c, 0x00000200 },
280 { 0x0090, 0x00000040 },
281 { 0x0100, 0x00000001 },
282 { 0x00c0, 0x00020001 },
283 { 0x00c8, 0x20042004 },
284 { 0x0380, 0x00020002 },
285 { 0x0390, 0x0000001f },
286 };
287
288 static const struct reg_config dbsc_config5[] = {
289 { 0x0244, 0x00000011 },
290 { 0x0290, 0x00000003 },
291 { 0x02a0, 0x0300c561 },
292 { 0x0290, 0x00000023 },
293 { 0x02a0, 0x00fcdb60 },
294 { 0x0290, 0x00000011 },
295 { 0x02a0, 0x1000040b },
296 { 0x0290, 0x00000012 },
297 { 0x02a0, 0x9d9cbb66 },
298 { 0x0290, 0x00000013 },
299 { 0x02a0, 0x1a868400 },
300 { 0x0290, 0x00000014 },
301 { 0x02a0, 0x300214d8 },
302 { 0x0290, 0x00000015 },
303 { 0x02a0, 0x00000d70 },
304 { 0x0290, 0x00000016 },
305 { 0x02a0, 0x00000006 },
306 { 0x0290, 0x00000017 },
307 { 0x02a0, 0x00000018 },
308 { 0x0290, 0x0000001a },
309 { 0x02a0, 0x910035c7 },
310 { 0x0290, 0x00000004 },
311 };
312
313 static const struct reg_config dbsc_config6[] = {
314 { 0x0290, 0x00000001 },
315 { 0x02a0, 0x00000181 },
316 { 0x0018, 0x11000000 },
317 { 0x0290, 0x00000004 },
318 };
319
320 static const struct reg_config dbsc_config7[] = {
321 { 0x0290, 0x00000001 },
322 { 0x02a0, 0x0000fe01 },
323 { 0x0304, 0x00000000 },
324 { 0x00f4, 0x01004c20 },
325 { 0x00f8, 0x014a00b9 },
326 { 0x00e0, 0x00000140 },
327 { 0x00e4, 0x00081860 },
328 { 0x00e8, 0x00010000 },
329 { 0x0290, 0x00000004 },
330 };
331
332 static const struct reg_config dbsc_config8[] = {
333 { 0x0014, 0x00000001 },
334 { 0x0290, 0x00000010 },
335 { 0x02a0, 0xf00464db },
336 { 0x4008, 0x00000000 },
337 { 0x4000, 0x00000000 },
338 { 0x0010, 0x00000001 },
339 { 0x0280, 0x00000000 },
340 };
341
342 static const u32 dbsc3_0_base = DBSC3_0_BASE;
343 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
344 static const u32 prr_base = 0xff000044;
345 const u16 prr_rev = readl(prr_base) & 0x7fff;
346 unsigned int i;
347
348 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
349 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
350 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
351 }
352
353 dbsc_wait(0x2a0);
354
355 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
356 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
357 writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
358 }
359
360 if (prr_rev == 0x4700) {
361 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
362 writel(dbsc_config3r0d0[i].val,
363 dbsc3_0_base | dbsc_config3r0d0[i].off);
364 }
365 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
366 writel(dbsc_config3r0d1[i].val,
367 dbsc3_1_base | dbsc_config3r0d1[i].off);
368 }
369 } else if (prr_rev != 0x4710) {
370 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
371 writel(dbsc_config3r2[i].val,
372 dbsc3_0_base | dbsc_config3r2[i].off);
373 writel(dbsc_config3r2[i].val,
374 dbsc3_1_base | dbsc_config3r2[i].off);
375 }
376 }
377
378 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
379 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
380 writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
381 }
382
383 dbsc_wait(0x240);
384
385 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
386 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
387 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
388 }
389
390 dbsc_wait(0x2a0);
391
392 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
393 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
394 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
395 }
396
397 dbsc_wait(0x2a0);
398
399 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
400 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
401 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
402 }
403
404 dbsc_wait(0x2a0);
405
406 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
407 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
408 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
409 }
410
411}
412
413static void spl_init_qspi(void)
414{
415 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
416
417 static const u32 qspi_base = 0xe6b10000;
418
419 writeb(0x08, qspi_base + 0x00);
420 writeb(0x00, qspi_base + 0x01);
421 writeb(0x06, qspi_base + 0x02);
422 writeb(0x01, qspi_base + 0x0a);
423 writeb(0x00, qspi_base + 0x0b);
424 writeb(0x00, qspi_base + 0x0c);
425 writeb(0x00, qspi_base + 0x0d);
426 writeb(0x00, qspi_base + 0x0e);
427
428 writew(0xe080, qspi_base + 0x10);
429
430 writeb(0xc0, qspi_base + 0x18);
431 writeb(0x00, qspi_base + 0x18);
432 writeb(0x00, qspi_base + 0x08);
433 writeb(0x48, qspi_base + 0x00);
434}
435
436void board_init_f(ulong dummy)
437{
438 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
439 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
440
441
442
443
444
445 writel(SD_97500KHZ, SD2CKCR);
446
447 spl_init_sys();
448 spl_init_pfc();
449 spl_init_gpio();
450 spl_init_lbsc();
451 spl_init_dbsc();
452 spl_init_qspi();
453}
454
455void spl_board_init(void)
456{
457
458 preloader_console_init();
459}
460
461void board_boot_order(u32 *spl_boot_list)
462{
463 const u32 jtag_magic = 0x1337c0de;
464 const u32 load_magic = 0xb33fc0de;
465
466
467
468
469
470 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
471 printf("JTAG boot detected!\n");
472
473 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
474 ;
475
476 spl_boot_list[0] = BOOT_DEVICE_RAM;
477 spl_boot_list[1] = BOOT_DEVICE_NONE;
478
479 return;
480 }
481
482
483 spl_boot_list[0] = BOOT_DEVICE_SPI;
484 spl_boot_list[1] = BOOT_DEVICE_UART;
485 spl_boot_list[2] = BOOT_DEVICE_NONE;
486}
487
488void reset_cpu(ulong addr)
489{
490}
491
