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16#include <common.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/arch/hardware.h>
19#include <asm/arch/mux.h>
20#include <asm/io.h>
21#include <i2c.h>
22#include "../common/board_detect.h"
23#include "board.h"
24
25static struct module_pin_mux uart0_pin_mux[] = {
26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
28 {-1},
29};
30
31static struct module_pin_mux uart1_pin_mux[] = {
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
34 {-1},
35};
36
37static struct module_pin_mux uart2_pin_mux[] = {
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},
40 {-1},
41};
42
43static struct module_pin_mux uart3_pin_mux[] = {
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},
46 {-1},
47};
48
49static struct module_pin_mux uart4_pin_mux[] = {
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},
52 {-1},
53};
54
55static struct module_pin_mux uart5_pin_mux[] = {
56 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},
57 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},
58 {-1},
59};
60
61static struct module_pin_mux mmc0_pin_mux[] = {
62 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
63 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
64 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
65 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
66 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
67 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
68 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},
69 {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},
70 {-1},
71};
72
73static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
74 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
75 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
76 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
77 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
78 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
79 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
80 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},
81 {-1},
82};
83
84static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
85 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
86 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
87 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
88 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
89 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
90 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
91 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},
92 {-1},
93};
94
95static struct module_pin_mux mmc1_pin_mux[] = {
96 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},
97 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},
98 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},
99 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},
100 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},
101 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},
102 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},
103 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},
104 {-1},
105};
106
107static struct module_pin_mux i2c0_pin_mux[] = {
108 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
109 PULLUDEN | SLEWCTRL)},
110 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
111 PULLUDEN | SLEWCTRL)},
112 {-1},
113};
114
115static struct module_pin_mux i2c1_pin_mux[] = {
116 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
117 PULLUDEN | SLEWCTRL)},
118 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
119 PULLUDEN | SLEWCTRL)},
120 {-1},
121};
122
123static struct module_pin_mux spi0_pin_mux[] = {
124 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},
125 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
126 PULLUDEN | PULLUP_EN)},
127 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},
128 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
129 PULLUDEN | PULLUP_EN)},
130 {-1},
131};
132
133static struct module_pin_mux gpio0_7_pin_mux[] = {
134 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},
135 {-1},
136};
137
138static struct module_pin_mux gpio0_18_pin_mux[] = {
139 {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)},
140 {-1},
141};
142
143static struct module_pin_mux rgmii1_pin_mux[] = {
144 {OFFSET(mii1_txen), MODE(2)},
145 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},
146 {OFFSET(mii1_txd3), MODE(2)},
147 {OFFSET(mii1_txd2), MODE(2)},
148 {OFFSET(mii1_txd1), MODE(2)},
149 {OFFSET(mii1_txd0), MODE(2)},
150 {OFFSET(mii1_txclk), MODE(2)},
151 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},
152 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},
153 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},
154 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},
155 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},
156 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
157 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
158 {-1},
159};
160
161static struct module_pin_mux mii1_pin_mux[] = {
162 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
163 {OFFSET(mii1_txen), MODE(0)},
164 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
165 {OFFSET(mii1_txd3), MODE(0)},
166 {OFFSET(mii1_txd2), MODE(0)},
167 {OFFSET(mii1_txd1), MODE(0)},
168 {OFFSET(mii1_txd0), MODE(0)},
169 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
170 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
171 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
172 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
173 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
174 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
175 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
176 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
177 {-1},
178};
179
180static struct module_pin_mux rmii1_pin_mux[] = {
181 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
182 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
183 {OFFSET(mii1_crs), MODE(1) | RXACTIVE},
184 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},
185 {OFFSET(mii1_txen), MODE(1)},
186 {OFFSET(mii1_txd1), MODE(1)},
187 {OFFSET(mii1_txd0), MODE(1)},
188 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},
189 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},
190 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},
191 {-1},
192};
193
194#ifdef CONFIG_NAND
195static struct module_pin_mux nand_pin_mux[] = {
196 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
197 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
198 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
199 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
200 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
201 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
202 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
203 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
204#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
205 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)},
206 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)},
207 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)},
208 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)},
209 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)},
210 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)},
211 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)},
212 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)},
213#endif
214 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
215 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
216 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
217 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
218 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
219 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
220 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
221 {-1},
222};
223#elif defined(CONFIG_NOR)
224static struct module_pin_mux bone_norcape_pin_mux[] = {
225 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS},
226 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS},
227 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS},
228 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS},
229 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS},
230 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS},
231 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS},
232 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS},
233 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE},
234 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE},
235 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE},
236 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE},
237 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE},
238 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE},
239 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE},
240 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE},
241 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE},
242 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},
243 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE},
244 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE},
245 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE},
246 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE},
247 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE},
248 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE},
249 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN},
250 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN},
251 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},
252 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},
253 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN},
254 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
255 {-1},
256};
257#endif
258
259static struct module_pin_mux uart3_icev2_pin_mux[] = {
260 {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},
261 {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN},
262 {-1},
263};
264
265#if defined(CONFIG_NOR_BOOT)
266void enable_norboot_pin_mux(void)
267{
268 configure_module_pin_mux(bone_norcape_pin_mux);
269}
270#endif
271
272void enable_uart0_pin_mux(void)
273{
274 configure_module_pin_mux(uart0_pin_mux);
275}
276
277void enable_uart1_pin_mux(void)
278{
279 configure_module_pin_mux(uart1_pin_mux);
280}
281
282void enable_uart2_pin_mux(void)
283{
284 configure_module_pin_mux(uart2_pin_mux);
285}
286
287void enable_uart3_pin_mux(void)
288{
289 configure_module_pin_mux(uart3_pin_mux);
290}
291
292void enable_uart4_pin_mux(void)
293{
294 configure_module_pin_mux(uart4_pin_mux);
295}
296
297void enable_uart5_pin_mux(void)
298{
299 configure_module_pin_mux(uart5_pin_mux);
300}
301
302void enable_i2c0_pin_mux(void)
303{
304 configure_module_pin_mux(i2c0_pin_mux);
305}
306
307
308
309
310
311
312#define PROFILE_NONE 0x0
313#define PROFILE_0 (1 << 0)
314#define PROFILE_1 (1 << 1)
315#define PROFILE_2 (1 << 2)
316#define PROFILE_3 (1 << 3)
317#define PROFILE_4 (1 << 4)
318#define PROFILE_5 (1 << 5)
319#define PROFILE_6 (1 << 6)
320#define PROFILE_7 (1 << 7)
321#define PROFILE_MASK 0x7
322#define PROFILE_ALL 0xFF
323
324
325#define I2C_CPLD_ADDR 0x35
326#define CFG_REG 0x10
327
328static unsigned short detect_daughter_board_profile(void)
329{
330 unsigned short val;
331
332#ifndef CONFIG_DM_I2C
333 if (i2c_probe(I2C_CPLD_ADDR))
334 return PROFILE_NONE;
335
336 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
337 return PROFILE_NONE;
338#else
339 struct udevice *dev = NULL;
340 int rc;
341
342 rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev);
343 if (rc)
344 return PROFILE_NONE;
345 rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
346 if (rc)
347 return PROFILE_NONE;
348#endif
349 return (1 << (val & PROFILE_MASK));
350}
351
352void enable_board_pin_mux(void)
353{
354
355 if (board_is_bone()) {
356
357 configure_module_pin_mux(mii1_pin_mux);
358 configure_module_pin_mux(mmc0_pin_mux);
359#if defined(CONFIG_NAND)
360 configure_module_pin_mux(nand_pin_mux);
361#elif defined(CONFIG_NOR)
362 configure_module_pin_mux(bone_norcape_pin_mux);
363#else
364 configure_module_pin_mux(mmc1_pin_mux);
365#endif
366 } else if (board_is_gp_evm()) {
367
368 unsigned short profile = detect_daughter_board_profile();
369 configure_module_pin_mux(rgmii1_pin_mux);
370 configure_module_pin_mux(mmc0_pin_mux);
371
372 if (profile & ~PROFILE_2)
373 configure_module_pin_mux(i2c1_pin_mux);
374
375#ifdef CONFIG_NAND
376 if (profile & ~(PROFILE_2 | PROFILE_3))
377 configure_module_pin_mux(nand_pin_mux);
378#endif
379 else if (profile == PROFILE_2) {
380 configure_module_pin_mux(mmc1_pin_mux);
381 configure_module_pin_mux(spi0_pin_mux);
382 }
383 } else if (board_is_idk()) {
384
385 configure_module_pin_mux(mii1_pin_mux);
386 configure_module_pin_mux(mmc0_no_cd_pin_mux);
387 } else if (board_is_evm_sk()) {
388
389 configure_module_pin_mux(i2c1_pin_mux);
390 configure_module_pin_mux(gpio0_7_pin_mux);
391 configure_module_pin_mux(rgmii1_pin_mux);
392 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
393 } else if (board_is_bone_lt()) {
394 if (board_is_bben()) {
395
396 configure_module_pin_mux(rgmii1_pin_mux);
397 } else {
398
399 configure_module_pin_mux(mii1_pin_mux);
400 }
401
402 configure_module_pin_mux(mii1_pin_mux);
403 configure_module_pin_mux(mmc0_pin_mux);
404#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
405 configure_module_pin_mux(nand_pin_mux);
406#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
407 configure_module_pin_mux(bone_norcape_pin_mux);
408#else
409 configure_module_pin_mux(mmc1_pin_mux);
410#endif
411 } else if (board_is_pb()) {
412 configure_module_pin_mux(mii1_pin_mux);
413 configure_module_pin_mux(mmc0_pin_mux);
414 } else if (board_is_icev2()) {
415 configure_module_pin_mux(mmc0_pin_mux);
416 configure_module_pin_mux(gpio0_18_pin_mux);
417 configure_module_pin_mux(uart3_icev2_pin_mux);
418 configure_module_pin_mux(rmii1_pin_mux);
419 configure_module_pin_mux(spi0_pin_mux);
420 } else {
421
422 puts("Bad EEPROM or unknown board, cannot configure pinmux.");
423 }
424}
425