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7#include <common.h>
8#include <i2c.h>
9#include <fsl_ddr_sdram.h>
10#include <fsl_ddr_dimm_params.h>
11
12void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
13{
14 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
15 sizeof(ddr2_spd_eeprom_t));
16}
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43typedef struct board_memctl_options {
44 uint16_t datarate_mhz_low;
45 uint16_t datarate_mhz_high;
46 uint8_t clk_adjust;
47 uint8_t cpo_override;
48 uint8_t write_data_delay;
49} board_memctl_options_t;
50
51static struct board_memctl_options bopts_ctrl[][2] = {
52 {
53
54 {
55
56 .datarate_mhz_low = 500,
57 .datarate_mhz_high = 750,
58 .clk_adjust = 5,
59 .cpo_override = 8,
60 .write_data_delay = 2,
61 },
62 {
63
64 .datarate_mhz_low = 750,
65 .datarate_mhz_high = 850,
66 .clk_adjust = 5,
67 .cpo_override = 9,
68 .write_data_delay = 2,
69 },
70 },
71 {
72
73 {
74
75 .datarate_mhz_low = 500,
76 .datarate_mhz_high = 750,
77 .clk_adjust = 5,
78 .cpo_override = 7,
79 .write_data_delay = 2,
80 },
81 {
82
83 .datarate_mhz_low = 750,
84 .datarate_mhz_high = 850,
85 .clk_adjust = 5,
86 .cpo_override = 8,
87 .write_data_delay = 2,
88 },
89 },
90};
91
92void fsl_ddr_board_options(memctl_options_t *popts,
93 dimm_params_t *pdimm,
94 unsigned int ctrl_num)
95{
96 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
97 sys_info_t sysinfo;
98 int i;
99 unsigned int datarate;
100
101 get_sys_info(&sysinfo);
102 datarate = get_ddr_freq(0) / 1000000;
103
104 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
105 if ((bopts[i].datarate_mhz_low <= datarate) &&
106 (bopts[i].datarate_mhz_high >= datarate)) {
107 debug("controller %d:\n", ctrl_num);
108 debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
109 debug(" cpo = %d\n", bopts[i].cpo_override);
110 debug(" write_data_delay = %d\n",
111 bopts[i].write_data_delay);
112 popts->clk_adjust = bopts[i].clk_adjust;
113 popts->cpo_override = bopts[i].cpo_override;
114 popts->write_data_delay = bopts[i].write_data_delay;
115 }
116 }
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122 popts->half_strength_driver_enable = 0;
123}
124