LXR uboot/drivers/clk/at91/clk-system.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2016 Atmel Corporation
   4 *               Wenyou.Yang <wenyou.yang@atmel.com>
   5 */
   6
   7#include <common.h>
   8#include <clk-uclass.h>
   9#include <dm.h>
  10#include <linux/io.h>
  11#include <mach/at91_pmc.h>
  12#include "pmc.h"
  13
  14#define SYSTEM_MAX_ID           31
  15
  16/**
  17 * at91_system_clk_bind() - for the system clock driver
  18 * Recursively bind its children as clk devices.
  19 *
  20 * @return: 0 on success, or negative error code on failure
  21 */
  22static int at91_system_clk_bind(struct udevice *dev)
  23{
  24        return at91_clk_sub_device_bind(dev, "system-clk");
  25}
  26
  27static const struct udevice_id at91_system_clk_match[] = {
  28        { .compatible = "atmel,at91rm9200-clk-system" },
  29        {}
  30};
  31
  32U_BOOT_DRIVER(at91_system_clk) = {
  33        .name = "at91-system-clk",
  34        .id = UCLASS_MISC,
  35        .of_match = at91_system_clk_match,
  36        .bind = at91_system_clk_bind,
  37};
  38
  39/*----------------------------------------------------------*/
  40
  41static inline int is_pck(int id)
  42{
  43        return (id >= 8) && (id <= 15);
  44}
  45
  46static ulong system_clk_get_rate(struct clk *clk)
  47{
  48        struct clk clk_dev;
  49        int ret;
  50
  51        ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  52        if (ret)
  53                return -EINVAL;
  54
  55        return clk_get_rate(&clk_dev);
  56}
  57
  58static ulong system_clk_set_rate(struct clk *clk, ulong rate)
  59{
  60        struct clk clk_dev;
  61        int ret;
  62
  63        ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  64        if (ret)
  65                return -EINVAL;
  66
  67        return clk_set_rate(&clk_dev, rate);
  68}
  69
  70static int system_clk_enable(struct clk *clk)
  71{
  72        struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  73        struct at91_pmc *pmc = plat->reg_base;
  74        u32 mask;
  75
  76        if (clk->id > SYSTEM_MAX_ID)
  77                return -EINVAL;
  78
  79        mask = BIT(clk->id);
  80
  81        writel(mask, &pmc->scer);
  82
  83        /**
  84         * For the programmable clocks the Ready status in the PMC
  85         * status register should be checked after enabling.
  86         * For other clocks this is unnecessary.
  87         */
  88        if (!is_pck(clk->id))
  89                return 0;
  90
  91        while (!(readl(&pmc->sr) & mask))
  92                ;
  93
  94        return 0;
  95}
  96
  97static struct clk_ops system_clk_ops = {
  98        .of_xlate = at91_clk_of_xlate,
  99        .get_rate = system_clk_get_rate,
 100        .set_rate = system_clk_set_rate,
 101        .enable = system_clk_enable,
 102};
 103
 104U_BOOT_DRIVER(system_clk) = {
 105        .name = "system-clk",
 106        .id = UCLASS_CLK,
 107        .probe = at91_clk_probe,
 108        .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 109        .ops = &system_clk_ops,
 110};
 111