LXR uboot/drivers/crypto/fsl/jr.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4 *
   5 */
   6
   7#ifndef __JR_H
   8#define __JR_H
   9
  10#include <linux/compiler.h>
  11
  12#define JR_SIZE 4
  13/* Timeout currently defined as 90 sec */
  14#define CONFIG_SEC_DEQ_TIMEOUT  90000000U
  15
  16#define DEFAULT_JR_ID           0
  17#define DEFAULT_JR_LIODN        0
  18#define DEFAULT_IRQ             0       /* Interrupts not to be configured */
  19
  20#define MCFGR_SWRST       ((uint32_t)(1)<<31) /* Software Reset */
  21#define MCFGR_DMA_RST     ((uint32_t)(1)<<28) /* DMA Reset */
  22#define MCFGR_PS_SHIFT          16
  23#define MCFGR_AWCACHE_SHIFT     8
  24#define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
  25#define MCFGR_ARCACHE_SHIFT     12
  26#define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
  27
  28#define JR_INTMASK        0x00000001
  29#define JRCR_RESET                  0x01
  30#define JRINT_ERR_HALT_INPROGRESS   0x4
  31#define JRINT_ERR_HALT_MASK         0xc
  32#define JRNSLIODN_SHIFT         16
  33#define JRNSLIODN_MASK          0x0fff0000
  34#define JRSLIODN_SHIFT          0
  35#define JRSLIODN_MASK           0x00000fff
  36#define JROWN_NS                0x00000008
  37#define JRMID_NS                0x00000001
  38
  39#define JQ_DEQ_ERR              -1
  40#define JQ_DEQ_TO_ERR           -2
  41#define JQ_ENQ_ERR              -3
  42
  43#define RNG4_MAX_HANDLES        2
  44
  45struct op_ring {
  46        phys_addr_t desc;
  47        uint32_t status;
  48} __packed;
  49
  50struct jr_info {
  51        void (*callback)(uint32_t status, void *arg);
  52        phys_addr_t desc_phys_addr;
  53        uint32_t desc_len;
  54        uint32_t op_done;
  55        void *arg;
  56};
  57
  58struct jobring {
  59        int jq_id;
  60        int irq;
  61        int liodn;
  62        /* Head is the index where software would enq the descriptor in
  63         * the i/p ring
  64         */
  65        int head;
  66        /* Tail index would be used by s/w ehile enqueuing to determine if
  67         * there is any space left in the s/w maintained i/p rings
  68         */
  69        /* Also in case of deq tail will be incremented only in case of
  70         * in-order job completion
  71         */
  72        int tail;
  73        /* Read index of the output ring. It may not match with tail in case
  74         * of out of order completetion
  75         */
  76        int read_idx;
  77        /* Write index to input ring. Would be always equal to head */
  78        int write_idx;
  79        /* Size of the rings. */
  80        int size;
  81        /* Op ring size aligned to cache line size */
  82        int op_size;
  83        /* The ip and output rings have to be accessed by SEC. So the
  84         * pointers will ahve to point to the housekeeping region provided
  85         * by SEC
  86         */
  87        /*Circular  Ring of i/p descriptors */
  88        dma_addr_t *input_ring;
  89        /* Circular Ring of o/p descriptors */
  90        /* Circula Ring containing info regarding descriptors in i/p
  91         * and o/p ring
  92         */
  93        /* This ring can be on the stack */
  94        struct jr_info info[JR_SIZE];
  95        struct op_ring *output_ring;
  96        /* Offset in CCSR to the SEC engine to which this JR belongs */
  97        uint32_t sec_offset;
  98
  99};
 100
 101struct result {
 102        int done;
 103        uint32_t status;
 104};
 105
 106void caam_jr_strstatus(u32 status);
 107int run_descriptor_jr(uint32_t *desc);
 108
 109#endif
 110