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6#include <common.h>
7#include <errno.h>
8#include <asm/io.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <imx_lpi2c.h>
12#include <asm/arch/sys_proto.h>
13#include <dm.h>
14#include <fdtdec.h>
15#include <i2c.h>
16
17#define LPI2C_FIFO_SIZE 4
18#define LPI2C_NACK_TOUT_MS 1
19#define LPI2C_TIMEOUT_MS 100
20
21static int bus_i2c_init(struct udevice *bus, int speed);
22
23
24int __weak init_i2c_power(unsigned i2c_num)
25{
26 return 0;
27}
28
29static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
30{
31 lpi2c_status_t result = LPI2C_SUCESS;
32 u32 status;
33
34 status = readl(®s->msr);
35
36 if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
37 result = LPI2C_BUSY;
38
39 return result;
40}
41
42static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
43{
44 lpi2c_status_t result = LPI2C_SUCESS;
45 u32 val, status;
46
47 status = readl(®s->msr);
48
49 status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
50 LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
51
52 if (status) {
53 if (status & LPI2C_MSR_PLTF_MASK)
54 result = LPI2C_PIN_LOW_TIMEOUT_ERR;
55 else if (status & LPI2C_MSR_ALF_MASK)
56 result = LPI2C_ARB_LOST_ERR;
57 else if (status & LPI2C_MSR_NDF_MASK)
58 result = LPI2C_NAK_ERR;
59 else if (status & LPI2C_MSR_FEF_MASK)
60 result = LPI2C_FIFO_ERR;
61
62
63 writel(0x7f00, ®s->msr);
64
65 val = readl(®s->mcr);
66 val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
67 writel(val, ®s->mcr);
68 }
69
70 return result;
71}
72
73static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
74{
75 lpi2c_status_t result = LPI2C_SUCESS;
76 u32 txcount = 0;
77 ulong start_time = get_timer(0);
78
79 do {
80 txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr));
81 txcount = LPI2C_FIFO_SIZE - txcount;
82 result = imx_lpci2c_check_clear_error(regs);
83 if (result) {
84 debug("i2c: wait for tx ready: result 0x%x\n", result);
85 return result;
86 }
87 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
88 debug("i2c: wait for tx ready: timeout\n");
89 return -1;
90 }
91 } while (!txcount);
92
93 return result;
94}
95
96static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
97{
98 struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
99 lpi2c_status_t result = LPI2C_SUCESS;
100
101
102 if (!len)
103 return result;
104
105 while (len--) {
106 result = bus_i2c_wait_for_tx_ready(regs);
107 if (result) {
108 debug("i2c: send wait for tx ready: %d\n", result);
109 return result;
110 }
111 writel(*txbuf++, ®s->mtdr);
112 }
113
114 return result;
115}
116
117static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
118{
119 struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
120 lpi2c_status_t result = LPI2C_SUCESS;
121 u32 val;
122 ulong start_time = get_timer(0);
123
124
125 if (!len)
126 return result;
127
128 result = bus_i2c_wait_for_tx_ready(regs);
129 if (result) {
130 debug("i2c: receive wait fot tx ready: %d\n", result);
131 return result;
132 }
133
134
135 writel(0x7f00, ®s->msr);
136
137 val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
138 writel(val, ®s->mtdr);
139
140 while (len--) {
141 do {
142 result = imx_lpci2c_check_clear_error(regs);
143 if (result) {
144 debug("i2c: receive check clear error: %d\n",
145 result);
146 return result;
147 }
148 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
149 debug("i2c: receive mrdr: timeout\n");
150 return -1;
151 }
152 val = readl(®s->mrdr);
153 } while (val & LPI2C_MRDR_RXEMPTY_MASK);
154 *rxbuf++ = LPI2C_MRDR_DATA(val);
155 }
156
157 return result;
158}
159
160static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
161{
162 lpi2c_status_t result;
163 struct imx_lpi2c_reg *regs =
164 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
165 u32 val;
166
167 result = imx_lpci2c_check_busy_bus(regs);
168 if (result) {
169 debug("i2c: start check busy bus: 0x%x\n", result);
170
171
172 bus_i2c_init(bus, 100000);
173 result = imx_lpci2c_check_busy_bus(regs);
174 if (result) {
175 printf("i2c: Error check busy bus: 0x%x\n", result);
176 return result;
177 }
178 }
179
180 writel(0x7f00, ®s->msr);
181
182 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
183 writel(val, ®s->mcfgr1);
184
185 result = bus_i2c_wait_for_tx_ready(regs);
186 if (result) {
187 debug("i2c: start wait for tx ready: 0x%x\n", result);
188 return result;
189 }
190
191 val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
192 writel(val, ®s->mtdr);
193
194 return result;
195}
196
197static int bus_i2c_stop(struct udevice *bus)
198{
199 lpi2c_status_t result;
200 struct imx_lpi2c_reg *regs =
201 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
202 u32 status;
203 ulong start_time;
204
205 result = bus_i2c_wait_for_tx_ready(regs);
206 if (result) {
207 debug("i2c: stop wait for tx ready: 0x%x\n", result);
208 return result;
209 }
210
211
212 writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr);
213
214 start_time = get_timer(0);
215 while (1) {
216 status = readl(®s->msr);
217 result = imx_lpci2c_check_clear_error(regs);
218
219 if (status & LPI2C_MSR_SDF_MASK) {
220
221 status &= LPI2C_MSR_SDF_MASK;
222 writel(status, ®s->msr);
223 break;
224 }
225
226 if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
227 debug("stop timeout\n");
228 return -ETIMEDOUT;
229 }
230 }
231
232 return result;
233}
234
235static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
236{
237 lpi2c_status_t result;
238
239 result = bus_i2c_start(bus, chip, 1);
240 if (result)
241 return result;
242 result = bus_i2c_receive(bus, buf, len);
243 if (result)
244 return result;
245
246 return result;
247}
248
249static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
250{
251 lpi2c_status_t result;
252
253 result = bus_i2c_start(bus, chip, 0);
254 if (result)
255 return result;
256 result = bus_i2c_send(bus, buf, len);
257 if (result)
258 return result;
259
260 return result;
261}
262
263
264u32 __weak imx_get_i2cclk(u32 i2c_num)
265{
266 return 0;
267}
268
269static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
270{
271 struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
272 struct imx_lpi2c_reg *regs;
273 u32 val;
274 u32 preescale = 0, best_pre = 0, clkhi = 0;
275 u32 best_clkhi = 0, abs_error = 0, rate;
276 u32 error = 0xffffffff;
277 u32 clock_rate;
278 bool mode;
279 int i;
280
281 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
282
283 if (IS_ENABLED(CONFIG_CLK)) {
284 clock_rate = clk_get_rate(&i2c_bus->per_clk);
285 if (clock_rate <= 0) {
286 dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
287 return clock_rate;
288 }
289 } else {
290 clock_rate = imx_get_i2cclk(bus->seq);
291 if (!clock_rate)
292 return -EPERM;
293 }
294
295 mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
296
297 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
298 writel(val | LPI2C_MCR_MEN(0), ®s->mcr);
299
300 for (preescale = 1; (preescale <= 128) &&
301 (error != 0); preescale = 2 * preescale) {
302 for (clkhi = 1; clkhi < 32; clkhi++) {
303 if (clkhi == 1)
304 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
305 else
306 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
307
308 abs_error = speed > rate ? speed - rate : rate - speed;
309
310 if (abs_error < error) {
311 best_pre = preescale;
312 best_clkhi = clkhi;
313 error = abs_error;
314 if (abs_error == 0)
315 break;
316 }
317 }
318 }
319
320
321 val = LPI2C_MCCR0_CLKHI(best_clkhi);
322 if (best_clkhi < 2)
323 val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
324 else
325 val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
326 LPI2C_MCCR0_DATAVD(best_clkhi / 2);
327 writel(val, ®s->mccr0);
328
329 for (i = 0; i < 8; i++) {
330 if (best_pre == (1 << i)) {
331 best_pre = i;
332 break;
333 }
334 }
335
336 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
337 writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1);
338
339 if (mode) {
340 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
341 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
342 }
343
344 return 0;
345}
346
347static int bus_i2c_init(struct udevice *bus, int speed)
348{
349 struct imx_lpi2c_reg *regs;
350 u32 val;
351 int ret;
352
353 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
354
355 writel(LPI2C_MCR_RST_MASK, ®s->mcr);
356 writel(0x0, ®s->mcr);
357
358 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr);
359
360 val = readl(®s->mcfgr0);
361 val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
362 LPI2C_MCFGR0_HRSEL_MASK));
363 val |= LPI2C_MCFGR0_HRPOL(0x1);
364 writel(val, ®s->mcfgr0);
365
366 val = readl(®s->mcfgr1);
367 val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
368 val |= LPI2C_MCFGR1_PINCFG(0x0);
369 val |= LPI2C_MCFGR1_IGNACK(0x0);
370 writel(val, ®s->mcfgr1);
371
372 ret = bus_i2c_set_bus_speed(bus, speed);
373
374
375 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
376 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
377
378 debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
379
380 return ret;
381}
382
383static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
384 u32 chip_flags)
385{
386 lpi2c_status_t result;
387
388 result = bus_i2c_start(bus, chip, 0);
389 if (result) {
390 bus_i2c_stop(bus);
391 bus_i2c_init(bus, 100000);
392 return result;
393 }
394
395 result = bus_i2c_stop(bus);
396 if (result)
397 bus_i2c_init(bus, 100000);
398
399 return result;
400}
401
402static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
403{
404 int ret = 0, ret_stop;
405
406 for (; nmsgs > 0; nmsgs--, msg++) {
407 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
408 if (msg->flags & I2C_M_RD)
409 ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
410 else {
411 ret = bus_i2c_write(bus, msg->addr, msg->buf,
412 msg->len);
413 if (ret)
414 break;
415 }
416 }
417
418 if (ret)
419 debug("i2c_write: error sending\n");
420
421 ret_stop = bus_i2c_stop(bus);
422 if (ret_stop)
423 debug("i2c_xfer: stop bus error\n");
424
425 ret |= ret_stop;
426
427 return ret;
428}
429
430static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
431{
432 return bus_i2c_set_bus_speed(bus, speed);
433}
434
435__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
436{
437 return 0;
438}
439
440static int imx_lpi2c_probe(struct udevice *bus)
441{
442 struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
443 fdt_addr_t addr;
444 int ret;
445
446 i2c_bus->driver_data = dev_get_driver_data(bus);
447
448 addr = devfdt_get_addr(bus);
449 if (addr == FDT_ADDR_T_NONE)
450 return -EINVAL;
451
452 i2c_bus->base = addr;
453 i2c_bus->index = bus->seq;
454 i2c_bus->bus = bus;
455
456
457 ret = init_i2c_power(bus->seq);
458 if (ret) {
459 debug("init_i2c_power err = %d\n", ret);
460 return ret;
461 }
462
463 if (IS_ENABLED(CONFIG_CLK)) {
464 ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
465 if (ret) {
466 dev_err(bus, "Failed to get per clk\n");
467 return ret;
468 }
469 ret = clk_enable(&i2c_bus->per_clk);
470 if (ret) {
471 dev_err(bus, "Failed to enable per clk\n");
472 return ret;
473 }
474 } else {
475
476 ret = enable_i2c_clk(1, bus->seq);
477 if (ret < 0)
478 return ret;
479 }
480
481 ret = bus_i2c_init(bus, 100000);
482 if (ret < 0)
483 return ret;
484
485 debug("i2c : controller bus %d at 0x%lx , speed %d: ",
486 bus->seq, i2c_bus->base,
487 i2c_bus->speed);
488
489 return 0;
490}
491
492static const struct dm_i2c_ops imx_lpi2c_ops = {
493 .xfer = imx_lpi2c_xfer,
494 .probe_chip = imx_lpi2c_probe_chip,
495 .set_bus_speed = imx_lpi2c_set_bus_speed,
496};
497
498static const struct udevice_id imx_lpi2c_ids[] = {
499 { .compatible = "fsl,imx7ulp-lpi2c", },
500 { .compatible = "fsl,imx8qm-lpi2c", },
501 {}
502};
503
504U_BOOT_DRIVER(imx_lpi2c) = {
505 .name = "imx_lpi2c",
506 .id = UCLASS_I2C,
507 .of_match = imx_lpi2c_ids,
508 .probe = imx_lpi2c_probe,
509 .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
510 .ops = &imx_lpi2c_ops,
511};
512
