LXR uboot/drivers/i2c/xilinx

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Xilinx AXI I2C driver
   4 *
   5 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
   6 *
   7 * Based on Linux 4.14.y i2c-xiic.c
   8 * Copyright (c) 2002-2007 Xilinx Inc.
   9 * Copyright (c) 2009-2010 Intel Corporation
  10 */
  11
  12#include <common.h>
  13#include <clk.h>
  14#include <dm.h>
  15#include <i2c.h>
  16#include <wait_bit.h>
  17#include <asm/io.h>
  18
  19struct xilinx_xiic_priv {
  20        void __iomem            *base;
  21        struct clk              clk;
  22};
  23
  24#define XIIC_MSB_OFFSET 0
  25#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
  26
  27/*
  28 * Register offsets in bytes from RegisterBase. Three is added to the
  29 * base offset to access LSB (IBM style) of the word
  30 */
  31#define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET)     /* Control Register   */
  32#define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET)     /* Status Register    */
  33#define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)     /* Data Tx Register   */
  34#define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)     /* Data Rx Register   */
  35#define XIIC_ADR_REG_OFFSET  (0x10+XIIC_REG_OFFSET)     /* Address Register   */
  36#define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)     /* Tx FIFO Occupancy  */
  37#define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)     /* Rx FIFO Occupancy  */
  38#define XIIC_TBA_REG_OFFSET  (0x1C+XIIC_REG_OFFSET)     /* 10 Bit Address reg */
  39#define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)     /* Rx FIFO Depth reg  */
  40#define XIIC_GPO_REG_OFFSET  (0x24+XIIC_REG_OFFSET)     /* Output Register    */
  41
  42/* Control Register masks */
  43#define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
  44#define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
  45#define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
  46#define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
  47#define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
  48#define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
  49#define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
  50
  51/* Status Register masks */
  52#define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
  53#define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
  54#define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
  55#define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
  56#define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
  57#define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
  58#define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
  59#define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80  /* 1 = Tx FIFO empty      */
  60
  61/* Interrupt Status Register masks    Interrupt occurs when...       */
  62#define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
  63#define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete */
  64#define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
  65#define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level */
  66#define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
  67#define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
  68#define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
  69#define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
  70
  71/* The following constants specify the depth of the FIFOs */
  72#define IIC_RX_FIFO_DEPTH         16    /* Rx fifo capacity               */
  73#define IIC_TX_FIFO_DEPTH         16    /* Tx fifo capacity               */
  74
  75/*
  76 * Tx Fifo upper bit masks.
  77 */
  78#define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
  79#define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */
  80
  81/*
  82 * The following constants define the register offsets for the Interrupt
  83 * registers. There are some holes in the memory map for reserved addresses
  84 * to allow other registers to be added and still match the memory map of the
  85 * interrupt controller registers
  86 */
  87#define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
  88#define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
  89#define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
  90#define XIIC_RESETR_OFFSET   0x40 /* Reset Register */
  91
  92#define XIIC_RESET_MASK             0xAUL
  93
  94static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags)
  95{
  96        return (addr << 1) | (flags & I2C_M_RD ? 1 : 0);
  97}
  98
  99static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask)
 100{
 101        u32 isr = readl(priv->base + XIIC_IISR_OFFSET);
 102
 103        writel(isr & mask, priv->base + XIIC_IISR_OFFSET);
 104}
 105
 106static int xiic_read_rx(struct xilinx_xiic_priv *priv,
 107                        struct i2c_msg *msg, int nmsgs)
 108{
 109        u8 bytes_in_fifo;
 110        u32 pos = 0;
 111        int i, ret;
 112
 113        while (pos < msg->len) {
 114                ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
 115                                     XIIC_SR_RX_FIFO_EMPTY_MASK, false,
 116                                     1000, true);
 117                if (ret)
 118                        return ret;
 119
 120                bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1;
 121
 122                if (bytes_in_fifo > msg->len)
 123                        bytes_in_fifo = msg->len;
 124
 125                for (i = 0; i < bytes_in_fifo; i++) {
 126                        msg->buf[pos++] = readb(priv->base +
 127                                                XIIC_DRR_REG_OFFSET);
 128                }
 129        }
 130
 131        return 0;
 132}
 133
 134static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv)
 135{
 136        /* return the actual space left in the FIFO */
 137        return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1;
 138}
 139
 140static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv,
 141                              struct i2c_msg *msg, int nmsgs)
 142{
 143        u8 fifo_space = xiic_tx_fifo_space(priv);
 144        int len = msg->len;
 145        u32 pos = 0;
 146
 147        len = (len > fifo_space) ? fifo_space : len;
 148
 149        while (len--) {
 150                u16 data = msg->buf[pos++];
 151
 152                if (pos == len && nmsgs == 1) {
 153                        /* last message in transfer -> STOP */
 154                        data |= XIIC_TX_DYN_STOP_MASK;
 155                }
 156                writew(data, priv->base + XIIC_DTR_REG_OFFSET);
 157        }
 158}
 159
 160static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr,
 161                                 u16 flags, u32 len, u32 nmsgs)
 162{
 163        struct xilinx_xiic_priv *priv = dev_get_priv(dev);
 164
 165        xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK);
 166
 167        if (!(flags & I2C_M_NOSTART)) {
 168                /* write the address */
 169                u16 data = i2c_8bit_addr_from_flags(addr, flags) |
 170                        XIIC_TX_DYN_START_MASK;
 171                if (nmsgs == 1 && len == 0)
 172                        /* no data and last message -> add STOP */
 173                        data |= XIIC_TX_DYN_STOP_MASK;
 174
 175                writew(data, priv->base + XIIC_DTR_REG_OFFSET);
 176        }
 177}
 178
 179static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg,
 180                                   u32 nmsgs)
 181{
 182        struct xilinx_xiic_priv *priv = dev_get_priv(dev);
 183        u8 rx_watermark;
 184
 185        /* Clear and enable Rx full interrupt. */
 186        xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
 187
 188        /* we want to get all but last byte, because the TX_ERROR IRQ is used
 189         * to inidicate error ACK on the address, and negative ack on the last
 190         * received byte, so to not mix them receive all but last.
 191         * In the case where there is only one byte to receive
 192         * we can check if ERROR and RX full is set at the same time
 193         */
 194        rx_watermark = msg->len;
 195        if (rx_watermark > IIC_RX_FIFO_DEPTH)
 196                rx_watermark = IIC_RX_FIFO_DEPTH;
 197
 198        writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET);
 199
 200        xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
 201
 202        xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
 203
 204        writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0),
 205               priv->base + XIIC_DTR_REG_OFFSET);
 206
 207        if (nmsgs == 1)
 208                /* very last, enable bus not busy as well */
 209                xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
 210
 211        return xiic_read_rx(priv, msg, nmsgs);
 212}
 213
 214static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg,
 215                                    int nmsgs)
 216{
 217        struct xilinx_xiic_priv *priv = dev_get_priv(dev);
 218        int ret;
 219
 220        xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
 221        xiic_fill_tx_fifo(priv, msg, nmsgs);
 222
 223        ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
 224                             XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true);
 225        if (ret)
 226                return ret;
 227
 228        /* Clear any pending Tx empty, Tx Error and then enable them. */
 229        xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
 230                           XIIC_INTR_BNB_MASK);
 231
 232        return 0;
 233}
 234
 235static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv)
 236{
 237        u8 sr;
 238
 239        for (sr = readb(priv->base + XIIC_SR_REG_OFFSET);
 240                !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
 241                sr = readb(priv->base + XIIC_SR_REG_OFFSET))
 242                readb(priv->base + XIIC_DRR_REG_OFFSET);
 243}
 244
 245static void xiic_reinit(struct xilinx_xiic_priv *priv)
 246{
 247        writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET);
 248
 249        /* Set receive Fifo depth to maximum (zero based). */
 250        writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET);
 251
 252        /* Reset Tx Fifo. */
 253        writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
 254
 255        /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
 256        writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET);
 257
 258        /* make sure RX fifo is empty */
 259        xiic_clear_rx_fifo(priv);
 260
 261        /* Disable interrupts */
 262        writel(0, priv->base + XIIC_DGIER_OFFSET);
 263
 264        xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK);
 265}
 266
 267static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 268{
 269        int ret = 0;
 270
 271        for (; nmsgs > 0; nmsgs--, msg++) {
 272                if (msg->flags & I2C_M_RD)
 273                        ret = xilinx_xiic_read_common(dev, msg, nmsgs);
 274                else
 275                        ret = xilinx_xiic_write_common(dev, msg, nmsgs);
 276
 277                if (ret)
 278                        return -EREMOTEIO;
 279        }
 280
 281        return ret;
 282}
 283
 284static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags)
 285{
 286        struct xilinx_xiic_priv *priv = dev_get_priv(dev);
 287        u32 reg;
 288        int ret;
 289
 290        xiic_reinit(priv);
 291
 292        xilinx_xiic_set_addr(dev, addr, 0, 0, 1);
 293        ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
 294                             XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
 295        if (ret)
 296                return ret;
 297
 298        reg = readl(priv->base + XIIC_IISR_OFFSET);
 299        if (reg & XIIC_INTR_TX_ERROR_MASK)
 300                return -ENODEV;
 301
 302        return 0;
 303}
 304
 305static int xilinx_xiic_set_speed(struct udevice *dev, uint speed)
 306{
 307        return 0;
 308}
 309
 310static int xilinx_xiic_probe(struct udevice *dev)
 311{
 312        struct xilinx_xiic_priv *priv = dev_get_priv(dev);
 313
 314        priv->base = dev_read_addr_ptr(dev);
 315
 316        writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
 317        xiic_reinit(priv);
 318
 319        return 0;
 320}
 321
 322static const struct dm_i2c_ops xilinx_xiic_ops = {
 323        .xfer           = xilinx_xiic_xfer,
 324        .probe_chip     = xilinx_xiic_probe_chip,
 325        .set_bus_speed  = xilinx_xiic_set_speed,
 326};
 327
 328static const struct udevice_id xilinx_xiic_ids[] = {
 329        { .compatible = "xlnx,xps-iic-2.00.a" },
 330        { }
 331};
 332
 333U_BOOT_DRIVER(xilinx_xiic) = {
 334        .name           = "xilinx_axi_i2c",
 335        .id             = UCLASS_I2C,
 336        .of_match       = xilinx_xiic_ids,
 337        .probe          = xilinx_xiic_probe,
 338        .priv_auto_alloc_size = sizeof(struct xilinx_xiic_priv),
 339        .ops            = &xilinx_xiic_ops,
 340};
 341