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9#include <common.h>
10#include <malloc.h>
11#include <mmc.h>
12#include <asm/io.h>
13#include <asm/unaligned.h>
14#include <errno.h>
15#include <mach/jz4780.h>
16#include <wait_bit.h>
17
18
19#define MSC_STRPCL 0x000
20#define MSC_STAT 0x004
21#define MSC_CLKRT 0x008
22#define MSC_CMDAT 0x00c
23#define MSC_RESTO 0x010
24#define MSC_RDTO 0x014
25#define MSC_BLKLEN 0x018
26#define MSC_NOB 0x01c
27#define MSC_SNOB 0x020
28#define MSC_IMASK 0x024
29#define MSC_IREG 0x028
30#define MSC_CMD 0x02c
31#define MSC_ARG 0x030
32#define MSC_RES 0x034
33#define MSC_RXFIFO 0x038
34#define MSC_TXFIFO 0x03c
35#define MSC_LPM 0x040
36#define MSC_DMAC 0x044
37#define MSC_DMANDA 0x048
38#define MSC_DMADA 0x04c
39#define MSC_DMALEN 0x050
40#define MSC_DMACMD 0x054
41#define MSC_CTRL2 0x058
42#define MSC_RTCNT 0x05c
43#define MSC_DBG 0x0fc
44
45
46#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
47#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
48#define MSC_STRPCL_START_READWAIT BIT(5)
49#define MSC_STRPCL_STOP_READWAIT BIT(4)
50#define MSC_STRPCL_RESET BIT(3)
51#define MSC_STRPCL_START_OP BIT(2)
52#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
53#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
54
55
56#define MSC_STAT_AUTO_CMD_DONE BIT(31)
57#define MSC_STAT_IS_RESETTING BIT(15)
58#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
59#define MSC_STAT_PRG_DONE BIT(13)
60#define MSC_STAT_DATA_TRAN_DONE BIT(12)
61#define MSC_STAT_END_CMD_RES BIT(11)
62#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
63#define MSC_STAT_IS_READWAIT BIT(9)
64#define MSC_STAT_CLK_EN BIT(8)
65#define MSC_STAT_DATA_FIFO_FULL BIT(7)
66#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
67#define MSC_STAT_CRC_RES_ERR BIT(5)
68#define MSC_STAT_CRC_READ_ERROR BIT(4)
69#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
70#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
71#define MSC_STAT_TIME_OUT_RES BIT(1)
72#define MSC_STAT_TIME_OUT_READ BIT(0)
73
74
75#define MSC_CLKRT_CLK_RATE_MASK 0x7
76
77
78#define MSC_CMDAT_IO_ABORT BIT(11)
79#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
80#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
81#define MSC_CMDAT_DMA_EN BIT(8)
82#define MSC_CMDAT_INIT BIT(7)
83#define MSC_CMDAT_BUSY BIT(6)
84#define MSC_CMDAT_STREAM_BLOCK BIT(5)
85#define MSC_CMDAT_WRITE BIT(4)
86#define MSC_CMDAT_DATA_EN BIT(3)
87#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
88#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0)
89#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0)
90#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0)
91#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0)
92#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0)
93#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0)
94#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0)
95
96
97#define MSC_IMASK_TIME_OUT_RES BIT(9)
98#define MSC_IMASK_TIME_OUT_READ BIT(8)
99#define MSC_IMASK_SDIO BIT(7)
100#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
101#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
102#define MSC_IMASK_END_CMD_RES BIT(2)
103#define MSC_IMASK_PRG_DONE BIT(1)
104#define MSC_IMASK_DATA_TRAN_DONE BIT(0)
105
106
107#define MSC_IREG_TIME_OUT_RES BIT(9)
108#define MSC_IREG_TIME_OUT_READ BIT(8)
109#define MSC_IREG_SDIO BIT(7)
110#define MSC_IREG_TXFIFO_WR_REQ BIT(6)
111#define MSC_IREG_RXFIFO_RD_REQ BIT(5)
112#define MSC_IREG_END_CMD_RES BIT(2)
113#define MSC_IREG_PRG_DONE BIT(1)
114#define MSC_IREG_DATA_TRAN_DONE BIT(0)
115
116struct jz_mmc_plat {
117 struct mmc_config cfg;
118 struct mmc mmc;
119};
120
121struct jz_mmc_priv {
122 void __iomem *regs;
123 u32 flags;
124
125#define JZ_MMC_BUS_WIDTH_MASK 0x3
126#define JZ_MMC_BUS_WIDTH_1 0x0
127#define JZ_MMC_BUS_WIDTH_4 0x2
128#define JZ_MMC_BUS_WIDTH_8 0x3
129#define JZ_MMC_SENT_INIT BIT(2)
130};
131
132static int jz_mmc_clock_rate(void)
133{
134 return 24000000;
135}
136
137static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
138 struct mmc_cmd *cmd, struct mmc_data *data)
139{
140 u32 stat, mask, cmdat = 0;
141 int i, ret;
142
143
144 writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
145 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
146 MSC_STAT_CLK_EN, false, 10000, false);
147 if (ret)
148 return ret;
149
150 writel(0, priv->regs + MSC_DMAC);
151
152
153 writel(cmd->cmdidx, priv->regs + MSC_CMD);
154 writel(cmd->cmdarg, priv->regs + MSC_ARG);
155
156 if (data) {
157
158 cmdat |= MSC_CMDAT_DATA_EN;
159 if (data->flags & MMC_DATA_WRITE)
160 cmdat |= MSC_CMDAT_WRITE;
161
162 writel(data->blocks, priv->regs + MSC_NOB);
163 writel(data->blocksize, priv->regs + MSC_BLKLEN);
164 } else {
165 writel(0, priv->regs + MSC_NOB);
166 writel(0, priv->regs + MSC_BLKLEN);
167 }
168
169
170 switch (cmd->resp_type) {
171 case MMC_RSP_NONE:
172 break;
173 case MMC_RSP_R1:
174 case MMC_RSP_R1b:
175 cmdat |= MSC_CMDAT_RESPONSE_R1;
176 break;
177 case MMC_RSP_R2:
178 cmdat |= MSC_CMDAT_RESPONSE_R2;
179 break;
180 case MMC_RSP_R3:
181 cmdat |= MSC_CMDAT_RESPONSE_R3;
182 break;
183 default:
184 break;
185 }
186
187 if (cmd->resp_type & MMC_RSP_BUSY)
188 cmdat |= MSC_CMDAT_BUSY;
189
190
191 if (!(priv->flags & JZ_MMC_SENT_INIT)) {
192 cmdat |= MSC_CMDAT_INIT;
193 priv->flags |= JZ_MMC_SENT_INIT;
194 }
195
196 cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
197
198
199 writel(cmdat, priv->regs + MSC_CMDAT);
200
201
202 mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
203 if (data) {
204 mask &= ~MSC_IMASK_DATA_TRAN_DONE;
205 if (data->flags & MMC_DATA_WRITE) {
206 mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
207 } else {
208 mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
209 MSC_IMASK_TIME_OUT_READ);
210 }
211 }
212 writel(mask, priv->regs + MSC_IMASK);
213
214
215 writel(0xffffffff, priv->regs + MSC_IREG);
216
217
218 writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
219 priv->regs + MSC_STRPCL);
220
221
222 for (i = 0; i < 100; i++) {
223 stat = readl(priv->regs + MSC_IREG);
224 stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
225 if (stat)
226 break;
227 mdelay(1);
228 }
229 writel(stat, priv->regs + MSC_IREG);
230 if (stat & MSC_IREG_TIME_OUT_RES)
231 return -ETIMEDOUT;
232
233 if (cmd->resp_type & MMC_RSP_PRESENT) {
234
235 if (cmd->resp_type & MMC_RSP_136) {
236 u16 a, b, c, i;
237
238 a = readw(priv->regs + MSC_RES);
239 for (i = 0; i < 4; i++) {
240 b = readw(priv->regs + MSC_RES);
241 c = readw(priv->regs + MSC_RES);
242 cmd->response[i] =
243 (a << 24) | (b << 8) | (c >> 8);
244 a = c;
245 }
246 } else {
247 cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
248 cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
249 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
250 }
251 }
252
253 if (data && (data->flags & MMC_DATA_WRITE)) {
254
255 int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
256 const void *buf = data->src;
257
258 while (sz--) {
259 u32 val = get_unaligned_le32(buf);
260
261 wait_for_bit_le32(priv->regs + MSC_IREG,
262 MSC_IREG_TXFIFO_WR_REQ,
263 true, 10000, false);
264 writel(val, priv->regs + MSC_TXFIFO);
265 buf += 4;
266 }
267 } else if (data && (data->flags & MMC_DATA_READ)) {
268
269 int sz = data->blocks * data->blocksize;
270 void *buf = data->dest;
271
272 do {
273 stat = readl(priv->regs + MSC_STAT);
274
275 if (stat & MSC_STAT_TIME_OUT_READ)
276 return -ETIMEDOUT;
277 if (stat & MSC_STAT_CRC_READ_ERROR)
278 return -EINVAL;
279 if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
280 udelay(10);
281 continue;
282 }
283 do {
284 u32 val = readl(priv->regs + MSC_RXFIFO);
285
286 if (sz == 1)
287 *(u8 *)buf = (u8)val;
288 else if (sz == 2)
289 put_unaligned_le16(val, buf);
290 else if (sz >= 4)
291 put_unaligned_le32(val, buf);
292 buf += 4;
293 sz -= 4;
294 stat = readl(priv->regs + MSC_STAT);
295 } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
296 } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
297 }
298
299 return 0;
300}
301
302static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
303{
304 u32 real_rate = jz_mmc_clock_rate();
305 u8 clk_div = 0;
306
307
308 while ((real_rate > mmc->clock) && (clk_div < 7)) {
309 real_rate >>= 1;
310 clk_div++;
311 }
312 writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
313
314
315 priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
316 if (mmc->bus_width == 8)
317 priv->flags |= JZ_MMC_BUS_WIDTH_8;
318 else if (mmc->bus_width == 4)
319 priv->flags |= JZ_MMC_BUS_WIDTH_4;
320 else
321 priv->flags |= JZ_MMC_BUS_WIDTH_1;
322
323 return 0;
324}
325
326static int jz_mmc_core_init(struct mmc *mmc)
327{
328 struct jz_mmc_priv *priv = mmc->priv;
329 int ret;
330
331
332 writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
333 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
334 MSC_STAT_IS_RESETTING, false, 10000, false);
335 if (ret)
336 return ret;
337
338
339 writel(0xffff, priv->regs + MSC_RESTO);
340 writel(0xffffffff, priv->regs + MSC_RDTO);
341
342
343 writel(0x1, priv->regs + MSC_LPM);
344
345 return 0;
346}
347
348#if !CONFIG_IS_ENABLED(DM_MMC)
349
350static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
351 struct mmc_data *data)
352{
353 struct jz_mmc_priv *priv = mmc->priv;
354
355 return jz_mmc_send_cmd(mmc, priv, cmd, data);
356}
357
358static int jz_mmc_legacy_set_ios(struct mmc *mmc)
359{
360 struct jz_mmc_priv *priv = mmc->priv;
361
362 return jz_mmc_set_ios(mmc, priv);
363};
364
365static const struct mmc_ops jz_msc_ops = {
366 .send_cmd = jz_mmc_legacy_send_cmd,
367 .set_ios = jz_mmc_legacy_set_ios,
368 .init = jz_mmc_core_init,
369};
370
371static struct jz_mmc_priv jz_mmc_priv_static;
372static struct jz_mmc_plat jz_mmc_plat_static = {
373 .cfg = {
374 .name = "MSC",
375 .ops = &jz_msc_ops,
376
377 .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
378 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
379 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
380 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
381
382 .f_min = 375000,
383 .f_max = 48000000,
384 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
385 },
386};
387
388int jz_mmc_init(void __iomem *base)
389{
390 struct mmc *mmc;
391
392 jz_mmc_priv_static.regs = base;
393
394 mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
395
396 return mmc ? 0 : -ENODEV;
397}
398
399#else
400
401#include <dm.h>
402DECLARE_GLOBAL_DATA_PTR;
403
404static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
405 struct mmc_data *data)
406{
407 struct jz_mmc_priv *priv = dev_get_priv(dev);
408 struct mmc *mmc = mmc_get_mmc_dev(dev);
409
410 return jz_mmc_send_cmd(mmc, priv, cmd, data);
411}
412
413static int jz_mmc_dm_set_ios(struct udevice *dev)
414{
415 struct jz_mmc_priv *priv = dev_get_priv(dev);
416 struct mmc *mmc = mmc_get_mmc_dev(dev);
417
418 return jz_mmc_set_ios(mmc, priv);
419};
420
421static const struct dm_mmc_ops jz_msc_ops = {
422 .send_cmd = jz_mmc_dm_send_cmd,
423 .set_ios = jz_mmc_dm_set_ios,
424};
425
426static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
427{
428 struct jz_mmc_priv *priv = dev_get_priv(dev);
429 struct jz_mmc_plat *plat = dev_get_platdata(dev);
430 struct mmc_config *cfg;
431 int ret;
432
433 priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
434 cfg = &plat->cfg;
435
436 cfg->name = "MSC";
437 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
438
439 ret = mmc_of_parse(dev, cfg);
440 if (ret < 0) {
441 dev_err(dev, "failed to parse host caps\n");
442 return ret;
443 }
444
445 cfg->f_min = 400000;
446 cfg->f_max = 52000000;
447
448 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
449 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
450
451 return 0;
452}
453
454static int jz_mmc_bind(struct udevice *dev)
455{
456 struct jz_mmc_plat *plat = dev_get_platdata(dev);
457
458 return mmc_bind(dev, &plat->mmc, &plat->cfg);
459}
460
461static int jz_mmc_probe(struct udevice *dev)
462{
463 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
464 struct jz_mmc_priv *priv = dev_get_priv(dev);
465 struct jz_mmc_plat *plat = dev_get_platdata(dev);
466
467 plat->mmc.priv = priv;
468 upriv->mmc = &plat->mmc;
469 return jz_mmc_core_init(&plat->mmc);
470}
471
472static const struct udevice_id jz_mmc_ids[] = {
473 { .compatible = "ingenic,jz4780-mmc" },
474 { }
475};
476
477U_BOOT_DRIVER(jz_mmc_drv) = {
478 .name = "jz_mmc",
479 .id = UCLASS_MMC,
480 .of_match = jz_mmc_ids,
481 .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
482 .bind = jz_mmc_bind,
483 .probe = jz_mmc_probe,
484 .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
485 .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
486 .ops = &jz_msc_ops,
487};
488#endif
489
