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9#include <config.h>
10#include <common.h>
11#include <command.h>
12#include <dm.h>
13#include <dm/device-internal.h>
14#include <errno.h>
15#include <mmc.h>
16#include <part.h>
17#include <power/regulator.h>
18#include <malloc.h>
19#include <memalign.h>
20#include <linux/list.h>
21#include <div64.h>
22#include "mmc_private.h"
23
24static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
25static int mmc_power_cycle(struct mmc *mmc);
26#if !CONFIG_IS_ENABLED(MMC_TINY)
27static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
28#endif
29
30#if !CONFIG_IS_ENABLED(DM_MMC)
31
32#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
33static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
34{
35 return -ENOSYS;
36}
37#endif
38
39__weak int board_mmc_getwp(struct mmc *mmc)
40{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
50 if (wp < 0) {
51 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
53 else
54 wp = 0;
55 }
56
57 return wp;
58}
59
60__weak int board_mmc_getcd(struct mmc *mmc)
61{
62 return -1;
63}
64#endif
65
66#ifdef CONFIG_MMC_TRACE
67void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
68{
69 printf("CMD_SEND:%d\n", cmd->cmdidx);
70 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
71}
72
73void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
75 int i;
76 u8 *ptr;
77
78 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
86 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
87 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
90 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
91 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
94 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
95 cmd->response[0]);
96 printf("\t\t \t\t 0x%08X \n",
97 cmd->response[1]);
98 printf("\t\t \t\t 0x%08X \n",
99 cmd->response[2]);
100 printf("\t\t \t\t 0x%08X \n",
101 cmd->response[3]);
102 printf("\n");
103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
110 printf("%02X ", *ptr--);
111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
121 }
122 }
123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
132#endif
133
134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
150 [MMC_HS_400] = "HS400 (200MHz)",
151 };
152
153 if (mode >= MMC_MODES_END)
154 return "Unknown mode";
155 else
156 return names[mode];
157}
158#endif
159
160static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
161{
162 static const int freqs[] = {
163 [MMC_LEGACY] = 25000000,
164 [SD_LEGACY] = 25000000,
165 [MMC_HS] = 26000000,
166 [SD_HS] = 50000000,
167 [MMC_HS_52] = 52000000,
168 [MMC_DDR_52] = 52000000,
169 [UHS_SDR12] = 25000000,
170 [UHS_SDR25] = 50000000,
171 [UHS_SDR50] = 100000000,
172 [UHS_DDR50] = 50000000,
173 [UHS_SDR104] = 208000000,
174 [MMC_HS_200] = 200000000,
175 [MMC_HS_400] = 200000000,
176 };
177
178 if (mode == MMC_LEGACY)
179 return mmc->legacy_speed;
180 else if (mode >= MMC_MODES_END)
181 return 0;
182 else
183 return freqs[mode];
184}
185
186static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
187{
188 mmc->selected_mode = mode;
189 mmc->tran_speed = mmc_mode2freq(mmc, mode);
190 mmc->ddr_mode = mmc_is_mode_ddr(mode);
191 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
192 mmc->tran_speed / 1000000);
193 return 0;
194}
195
196#if !CONFIG_IS_ENABLED(DM_MMC)
197int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
198{
199 int ret;
200
201 mmmc_trace_before_send(mmc, cmd);
202 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
203 mmmc_trace_after_send(mmc, cmd, ret);
204
205 return ret;
206}
207#endif
208
209int mmc_send_status(struct mmc *mmc, int timeout)
210{
211 struct mmc_cmd cmd;
212 int err, retries = 5;
213
214 cmd.cmdidx = MMC_CMD_SEND_STATUS;
215 cmd.resp_type = MMC_RSP_R1;
216 if (!mmc_host_is_spi(mmc))
217 cmd.cmdarg = mmc->rca << 16;
218
219 while (1) {
220 err = mmc_send_cmd(mmc, &cmd, NULL);
221 if (!err) {
222 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
223 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
224 MMC_STATE_PRG)
225 break;
226
227 if (cmd.response[0] & MMC_STATUS_MASK) {
228#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
229 pr_err("Status Error: 0x%08X\n",
230 cmd.response[0]);
231#endif
232 return -ECOMM;
233 }
234 } else if (--retries < 0)
235 return err;
236
237 if (timeout-- <= 0)
238 break;
239
240 udelay(1000);
241 }
242
243 mmc_trace_state(mmc, &cmd);
244 if (timeout <= 0) {
245#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
246 pr_err("Timeout waiting card ready\n");
247#endif
248 return -ETIMEDOUT;
249 }
250
251 return 0;
252}
253
254int mmc_set_blocklen(struct mmc *mmc, int len)
255{
256 struct mmc_cmd cmd;
257 int err;
258
259 if (mmc->ddr_mode)
260 return 0;
261
262 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
263 cmd.resp_type = MMC_RSP_R1;
264 cmd.cmdarg = len;
265
266 err = mmc_send_cmd(mmc, &cmd, NULL);
267
268#ifdef CONFIG_MMC_QUIRKS
269 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
270 int retries = 4;
271
272
273
274
275 do {
276 err = mmc_send_cmd(mmc, &cmd, NULL);
277 if (!err)
278 break;
279 } while (retries--);
280 }
281#endif
282
283 return err;
284}
285
286#ifdef MMC_SUPPORTS_TUNING
287static const u8 tuning_blk_pattern_4bit[] = {
288 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
289 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
290 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
291 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
292 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
293 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
294 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
295 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
296};
297
298static const u8 tuning_blk_pattern_8bit[] = {
299 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
300 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
301 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
302 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
303 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
304 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
305 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
306 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
307 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
308 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
309 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
310 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
311 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
312 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
313 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
314 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
315};
316
317int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
318{
319 struct mmc_cmd cmd;
320 struct mmc_data data;
321 const u8 *tuning_block_pattern;
322 int size, err;
323
324 if (mmc->bus_width == 8) {
325 tuning_block_pattern = tuning_blk_pattern_8bit;
326 size = sizeof(tuning_blk_pattern_8bit);
327 } else if (mmc->bus_width == 4) {
328 tuning_block_pattern = tuning_blk_pattern_4bit;
329 size = sizeof(tuning_blk_pattern_4bit);
330 } else {
331 return -EINVAL;
332 }
333
334 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
335
336 cmd.cmdidx = opcode;
337 cmd.cmdarg = 0;
338 cmd.resp_type = MMC_RSP_R1;
339
340 data.dest = (void *)data_buf;
341 data.blocks = 1;
342 data.blocksize = size;
343 data.flags = MMC_DATA_READ;
344
345 err = mmc_send_cmd(mmc, &cmd, &data);
346 if (err)
347 return err;
348
349 if (memcmp(data_buf, tuning_block_pattern, size))
350 return -EIO;
351
352 return 0;
353}
354#endif
355
356static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
357 lbaint_t blkcnt)
358{
359 struct mmc_cmd cmd;
360 struct mmc_data data;
361
362 if (blkcnt > 1)
363 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
364 else
365 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
366
367 if (mmc->high_capacity)
368 cmd.cmdarg = start;
369 else
370 cmd.cmdarg = start * mmc->read_bl_len;
371
372 cmd.resp_type = MMC_RSP_R1;
373
374 data.dest = dst;
375 data.blocks = blkcnt;
376 data.blocksize = mmc->read_bl_len;
377 data.flags = MMC_DATA_READ;
378
379 if (mmc_send_cmd(mmc, &cmd, &data))
380 return 0;
381
382 if (blkcnt > 1) {
383 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
384 cmd.cmdarg = 0;
385 cmd.resp_type = MMC_RSP_R1b;
386 if (mmc_send_cmd(mmc, &cmd, NULL)) {
387#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
388 pr_err("mmc fail to send stop cmd\n");
389#endif
390 return 0;
391 }
392 }
393
394 return blkcnt;
395}
396
397#if CONFIG_IS_ENABLED(BLK)
398ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
399#else
400ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
401 void *dst)
402#endif
403{
404#if CONFIG_IS_ENABLED(BLK)
405 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
406#endif
407 int dev_num = block_dev->devnum;
408 int err;
409 lbaint_t cur, blocks_todo = blkcnt;
410
411 if (blkcnt == 0)
412 return 0;
413
414 struct mmc *mmc = find_mmc_device(dev_num);
415 if (!mmc)
416 return 0;
417
418 if (CONFIG_IS_ENABLED(MMC_TINY))
419 err = mmc_switch_part(mmc, block_dev->hwpart);
420 else
421 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
422
423 if (err < 0)
424 return 0;
425
426 if ((start + blkcnt) > block_dev->lba) {
427#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
428 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
429 start + blkcnt, block_dev->lba);
430#endif
431 return 0;
432 }
433
434 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
435 pr_debug("%s: Failed to set blocklen\n", __func__);
436 return 0;
437 }
438
439 do {
440 cur = (blocks_todo > mmc->cfg->b_max) ?
441 mmc->cfg->b_max : blocks_todo;
442 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
443 pr_debug("%s: Failed to read blocks\n", __func__);
444 return 0;
445 }
446 blocks_todo -= cur;
447 start += cur;
448 dst += cur * mmc->read_bl_len;
449 } while (blocks_todo > 0);
450
451 return blkcnt;
452}
453
454static int mmc_go_idle(struct mmc *mmc)
455{
456 struct mmc_cmd cmd;
457 int err;
458
459 udelay(1000);
460
461 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
462 cmd.cmdarg = 0;
463 cmd.resp_type = MMC_RSP_NONE;
464
465 err = mmc_send_cmd(mmc, &cmd, NULL);
466
467 if (err)
468 return err;
469
470 udelay(2000);
471
472 return 0;
473}
474
475#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
476static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
477{
478 struct mmc_cmd cmd;
479 int err = 0;
480
481
482
483
484
485 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
486 return mmc_set_signal_voltage(mmc, signal_voltage);
487
488 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
489 cmd.cmdarg = 0;
490 cmd.resp_type = MMC_RSP_R1;
491
492 err = mmc_send_cmd(mmc, &cmd, NULL);
493 if (err)
494 return err;
495
496 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
497 return -EIO;
498
499
500
501
502
503 err = mmc_wait_dat0(mmc, 0, 100);
504 if (err == -ENOSYS)
505 udelay(100);
506 else if (err)
507 return -ETIMEDOUT;
508
509
510
511
512
513 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
514
515 err = mmc_set_signal_voltage(mmc, signal_voltage);
516 if (err)
517 return err;
518
519
520 mdelay(10);
521 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
522
523
524
525
526
527 err = mmc_wait_dat0(mmc, 1, 1000);
528 if (err == -ENOSYS)
529 udelay(1000);
530 else if (err)
531 return -ETIMEDOUT;
532
533 return 0;
534}
535#endif
536
537static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
538{
539 int timeout = 1000;
540 int err;
541 struct mmc_cmd cmd;
542
543 while (1) {
544 cmd.cmdidx = MMC_CMD_APP_CMD;
545 cmd.resp_type = MMC_RSP_R1;
546 cmd.cmdarg = 0;
547
548 err = mmc_send_cmd(mmc, &cmd, NULL);
549
550 if (err)
551 return err;
552
553 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
554 cmd.resp_type = MMC_RSP_R3;
555
556
557
558
559
560
561
562
563 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
564 (mmc->cfg->voltages & 0xff8000);
565
566 if (mmc->version == SD_VERSION_2)
567 cmd.cmdarg |= OCR_HCS;
568
569 if (uhs_en)
570 cmd.cmdarg |= OCR_S18R;
571
572 err = mmc_send_cmd(mmc, &cmd, NULL);
573
574 if (err)
575 return err;
576
577 if (cmd.response[0] & OCR_BUSY)
578 break;
579
580 if (timeout-- <= 0)
581 return -EOPNOTSUPP;
582
583 udelay(1000);
584 }
585
586 if (mmc->version != SD_VERSION_2)
587 mmc->version = SD_VERSION_1_0;
588
589 if (mmc_host_is_spi(mmc)) {
590 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
591 cmd.resp_type = MMC_RSP_R3;
592 cmd.cmdarg = 0;
593
594 err = mmc_send_cmd(mmc, &cmd, NULL);
595
596 if (err)
597 return err;
598 }
599
600 mmc->ocr = cmd.response[0];
601
602#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
603 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
604 == 0x41000000) {
605 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
606 if (err)
607 return err;
608 }
609#endif
610
611 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
612 mmc->rca = 0;
613
614 return 0;
615}
616
617static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
618{
619 struct mmc_cmd cmd;
620 int err;
621
622 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
623 cmd.resp_type = MMC_RSP_R3;
624 cmd.cmdarg = 0;
625 if (use_arg && !mmc_host_is_spi(mmc))
626 cmd.cmdarg = OCR_HCS |
627 (mmc->cfg->voltages &
628 (mmc->ocr & OCR_VOLTAGE_MASK)) |
629 (mmc->ocr & OCR_ACCESS_MODE);
630
631 err = mmc_send_cmd(mmc, &cmd, NULL);
632 if (err)
633 return err;
634 mmc->ocr = cmd.response[0];
635 return 0;
636}
637
638static int mmc_send_op_cond(struct mmc *mmc)
639{
640 int err, i;
641
642
643 mmc_go_idle(mmc);
644
645
646 for (i = 0; i < 2; i++) {
647 err = mmc_send_op_cond_iter(mmc, i != 0);
648 if (err)
649 return err;
650
651
652 if (mmc->ocr & OCR_BUSY)
653 break;
654 }
655 mmc->op_cond_pending = 1;
656 return 0;
657}
658
659static int mmc_complete_op_cond(struct mmc *mmc)
660{
661 struct mmc_cmd cmd;
662 int timeout = 1000;
663 ulong start;
664 int err;
665
666 mmc->op_cond_pending = 0;
667 if (!(mmc->ocr & OCR_BUSY)) {
668
669 mmc_go_idle(mmc);
670
671 start = get_timer(0);
672 while (1) {
673 err = mmc_send_op_cond_iter(mmc, 1);
674 if (err)
675 return err;
676 if (mmc->ocr & OCR_BUSY)
677 break;
678 if (get_timer(start) > timeout)
679 return -EOPNOTSUPP;
680 udelay(100);
681 }
682 }
683
684 if (mmc_host_is_spi(mmc)) {
685 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
686 cmd.resp_type = MMC_RSP_R3;
687 cmd.cmdarg = 0;
688
689 err = mmc_send_cmd(mmc, &cmd, NULL);
690
691 if (err)
692 return err;
693
694 mmc->ocr = cmd.response[0];
695 }
696
697 mmc->version = MMC_VERSION_UNKNOWN;
698
699 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
700 mmc->rca = 1;
701
702 return 0;
703}
704
705
706static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
707{
708 struct mmc_cmd cmd;
709 struct mmc_data data;
710 int err;
711
712
713 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
714 cmd.resp_type = MMC_RSP_R1;
715 cmd.cmdarg = 0;
716
717 data.dest = (char *)ext_csd;
718 data.blocks = 1;
719 data.blocksize = MMC_MAX_BLOCK_LEN;
720 data.flags = MMC_DATA_READ;
721
722 err = mmc_send_cmd(mmc, &cmd, &data);
723
724 return err;
725}
726
727int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
728{
729 struct mmc_cmd cmd;
730 int timeout = 1000;
731 int retries = 3;
732 int ret;
733
734 cmd.cmdidx = MMC_CMD_SWITCH;
735 cmd.resp_type = MMC_RSP_R1b;
736 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
737 (index << 16) |
738 (value << 8);
739
740 while (retries > 0) {
741 ret = mmc_send_cmd(mmc, &cmd, NULL);
742
743
744 if (!ret) {
745 ret = mmc_send_status(mmc, timeout);
746 return ret;
747 }
748
749 retries--;
750 }
751
752 return ret;
753
754}
755
756#if !CONFIG_IS_ENABLED(MMC_TINY)
757static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
758{
759 int err;
760 int speed_bits;
761
762 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
763
764 switch (mode) {
765 case MMC_HS:
766 case MMC_HS_52:
767 case MMC_DDR_52:
768 speed_bits = EXT_CSD_TIMING_HS;
769 break;
770#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
771 case MMC_HS_200:
772 speed_bits = EXT_CSD_TIMING_HS200;
773 break;
774#endif
775#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
776 case MMC_HS_400:
777 speed_bits = EXT_CSD_TIMING_HS400;
778 break;
779#endif
780 case MMC_LEGACY:
781 speed_bits = EXT_CSD_TIMING_LEGACY;
782 break;
783 default:
784 return -EINVAL;
785 }
786 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
787 speed_bits);
788 if (err)
789 return err;
790
791 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
792
793 err = mmc_send_ext_csd(mmc, test_csd);
794 if (err)
795 return err;
796
797
798 if (!test_csd[EXT_CSD_HS_TIMING])
799 return -ENOTSUPP;
800 }
801
802 return 0;
803}
804
805static int mmc_get_capabilities(struct mmc *mmc)
806{
807 u8 *ext_csd = mmc->ext_csd;
808 char cardtype;
809
810 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
811
812 if (mmc_host_is_spi(mmc))
813 return 0;
814
815
816 if (mmc->version < MMC_VERSION_4)
817 return 0;
818
819 if (!ext_csd) {
820 pr_err("No ext_csd found!\n");
821 return -ENOTSUPP;
822 }
823
824 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
825
826 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
827 mmc->cardtype = cardtype;
828
829#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
830 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
831 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
832 mmc->card_caps |= MMC_MODE_HS200;
833 }
834#endif
835#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
836 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
837 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
838 mmc->card_caps |= MMC_MODE_HS400;
839 }
840#endif
841 if (cardtype & EXT_CSD_CARD_TYPE_52) {
842 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
843 mmc->card_caps |= MMC_MODE_DDR_52MHz;
844 mmc->card_caps |= MMC_MODE_HS_52MHz;
845 }
846 if (cardtype & EXT_CSD_CARD_TYPE_26)
847 mmc->card_caps |= MMC_MODE_HS;
848
849 return 0;
850}
851#endif
852
853static int mmc_set_capacity(struct mmc *mmc, int part_num)
854{
855 switch (part_num) {
856 case 0:
857 mmc->capacity = mmc->capacity_user;
858 break;
859 case 1:
860 case 2:
861 mmc->capacity = mmc->capacity_boot;
862 break;
863 case 3:
864 mmc->capacity = mmc->capacity_rpmb;
865 break;
866 case 4:
867 case 5:
868 case 6:
869 case 7:
870 mmc->capacity = mmc->capacity_gp[part_num - 4];
871 break;
872 default:
873 return -1;
874 }
875
876 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
877
878 return 0;
879}
880
881#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
882static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
883{
884 int forbidden = 0;
885 bool change = false;
886
887 if (part_num & PART_ACCESS_MASK)
888 forbidden = MMC_CAP(MMC_HS_200);
889
890 if (MMC_CAP(mmc->selected_mode) & forbidden) {
891 pr_debug("selected mode (%s) is forbidden for part %d\n",
892 mmc_mode_name(mmc->selected_mode), part_num);
893 change = true;
894 } else if (mmc->selected_mode != mmc->best_mode) {
895 pr_debug("selected mode is not optimal\n");
896 change = true;
897 }
898
899 if (change)
900 return mmc_select_mode_and_width(mmc,
901 mmc->card_caps & ~forbidden);
902
903 return 0;
904}
905#else
906static inline int mmc_boot_part_access_chk(struct mmc *mmc,
907 unsigned int part_num)
908{
909 return 0;
910}
911#endif
912
913int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
914{
915 int ret;
916
917 ret = mmc_boot_part_access_chk(mmc, part_num);
918 if (ret)
919 return ret;
920
921 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
922 (mmc->part_config & ~PART_ACCESS_MASK)
923 | (part_num & PART_ACCESS_MASK));
924
925
926
927
928
929 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
930 ret = mmc_set_capacity(mmc, part_num);
931 mmc_get_blk_desc(mmc)->hwpart = part_num;
932 }
933
934 return ret;
935}
936
937#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
938int mmc_hwpart_config(struct mmc *mmc,
939 const struct mmc_hwpart_conf *conf,
940 enum mmc_hwpart_conf_mode mode)
941{
942 u8 part_attrs = 0;
943 u32 enh_size_mult;
944 u32 enh_start_addr;
945 u32 gp_size_mult[4];
946 u32 max_enh_size_mult;
947 u32 tot_enh_size_mult = 0;
948 u8 wr_rel_set;
949 int i, pidx, err;
950 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
951
952 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
953 return -EINVAL;
954
955 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
956 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
957 return -EMEDIUMTYPE;
958 }
959
960 if (!(mmc->part_support & PART_SUPPORT)) {
961 pr_err("Card does not support partitioning\n");
962 return -EMEDIUMTYPE;
963 }
964
965 if (!mmc->hc_wp_grp_size) {
966 pr_err("Card does not define HC WP group size\n");
967 return -EMEDIUMTYPE;
968 }
969
970
971 if (conf->user.enh_size) {
972 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
973 conf->user.enh_start % mmc->hc_wp_grp_size) {
974 pr_err("User data enhanced area not HC WP group "
975 "size aligned\n");
976 return -EINVAL;
977 }
978 part_attrs |= EXT_CSD_ENH_USR;
979 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
980 if (mmc->high_capacity) {
981 enh_start_addr = conf->user.enh_start;
982 } else {
983 enh_start_addr = (conf->user.enh_start << 9);
984 }
985 } else {
986 enh_size_mult = 0;
987 enh_start_addr = 0;
988 }
989 tot_enh_size_mult += enh_size_mult;
990
991 for (pidx = 0; pidx < 4; pidx++) {
992 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
993 pr_err("GP%i partition not HC WP group size "
994 "aligned\n", pidx+1);
995 return -EINVAL;
996 }
997 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
998 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
999 part_attrs |= EXT_CSD_ENH_GP(pidx);
1000 tot_enh_size_mult += gp_size_mult[pidx];
1001 }
1002 }
1003
1004 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1005 pr_err("Card does not support enhanced attribute\n");
1006 return -EMEDIUMTYPE;
1007 }
1008
1009 err = mmc_send_ext_csd(mmc, ext_csd);
1010 if (err)
1011 return err;
1012
1013 max_enh_size_mult =
1014 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1015 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1016 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1017 if (tot_enh_size_mult > max_enh_size_mult) {
1018 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1019 tot_enh_size_mult, max_enh_size_mult);
1020 return -EMEDIUMTYPE;
1021 }
1022
1023
1024
1025
1026
1027 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1028 if (conf->user.wr_rel_change) {
1029 if (conf->user.wr_rel_set)
1030 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1031 else
1032 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1033 }
1034 for (pidx = 0; pidx < 4; pidx++) {
1035 if (conf->gp_part[pidx].wr_rel_change) {
1036 if (conf->gp_part[pidx].wr_rel_set)
1037 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1038 else
1039 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1040 }
1041 }
1042
1043 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1044 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1045 puts("Card does not support host controlled partition write "
1046 "reliability settings\n");
1047 return -EMEDIUMTYPE;
1048 }
1049
1050 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1051 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1052 pr_err("Card already partitioned\n");
1053 return -EPERM;
1054 }
1055
1056 if (mode == MMC_HWPART_CONF_CHECK)
1057 return 0;
1058
1059
1060 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1061 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1062 EXT_CSD_ERASE_GROUP_DEF, 1);
1063
1064 if (err)
1065 return err;
1066
1067 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1068
1069
1070 mmc->erase_grp_size =
1071 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1072
1073 }
1074
1075
1076 for (i = 0; i < 4; i++) {
1077 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1078 EXT_CSD_ENH_START_ADDR+i,
1079 (enh_start_addr >> (i*8)) & 0xFF);
1080 if (err)
1081 return err;
1082 }
1083 for (i = 0; i < 3; i++) {
1084 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1085 EXT_CSD_ENH_SIZE_MULT+i,
1086 (enh_size_mult >> (i*8)) & 0xFF);
1087 if (err)
1088 return err;
1089 }
1090 for (pidx = 0; pidx < 4; pidx++) {
1091 for (i = 0; i < 3; i++) {
1092 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1093 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1094 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1095 if (err)
1096 return err;
1097 }
1098 }
1099 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1100 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1101 if (err)
1102 return err;
1103
1104 if (mode == MMC_HWPART_CONF_SET)
1105 return 0;
1106
1107
1108
1109
1110
1111 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1112 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1113 EXT_CSD_WR_REL_SET, wr_rel_set);
1114 if (err)
1115 return err;
1116 }
1117
1118
1119
1120
1121
1122
1123 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1124 EXT_CSD_PARTITION_SETTING,
1125 EXT_CSD_PARTITION_SETTING_COMPLETED);
1126 if (err)
1127 return err;
1128
1129 return 0;
1130}
1131#endif
1132
1133#if !CONFIG_IS_ENABLED(DM_MMC)
1134int mmc_getcd(struct mmc *mmc)
1135{
1136 int cd;
1137
1138 cd = board_mmc_getcd(mmc);
1139
1140 if (cd < 0) {
1141 if (mmc->cfg->ops->getcd)
1142 cd = mmc->cfg->ops->getcd(mmc);
1143 else
1144 cd = 1;
1145 }
1146
1147 return cd;
1148}
1149#endif
1150
1151#if !CONFIG_IS_ENABLED(MMC_TINY)
1152static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1153{
1154 struct mmc_cmd cmd;
1155 struct mmc_data data;
1156
1157
1158 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1159 cmd.resp_type = MMC_RSP_R1;
1160 cmd.cmdarg = (mode << 31) | 0xffffff;
1161 cmd.cmdarg &= ~(0xf << (group * 4));
1162 cmd.cmdarg |= value << (group * 4);
1163
1164 data.dest = (char *)resp;
1165 data.blocksize = 64;
1166 data.blocks = 1;
1167 data.flags = MMC_DATA_READ;
1168
1169 return mmc_send_cmd(mmc, &cmd, &data);
1170}
1171
1172static int sd_get_capabilities(struct mmc *mmc)
1173{
1174 int err;
1175 struct mmc_cmd cmd;
1176 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1177 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1178 struct mmc_data data;
1179 int timeout;
1180#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1181 u32 sd3_bus_mode;
1182#endif
1183
1184 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1185
1186 if (mmc_host_is_spi(mmc))
1187 return 0;
1188
1189
1190 cmd.cmdidx = MMC_CMD_APP_CMD;
1191 cmd.resp_type = MMC_RSP_R1;
1192 cmd.cmdarg = mmc->rca << 16;
1193
1194 err = mmc_send_cmd(mmc, &cmd, NULL);
1195
1196 if (err)
1197 return err;
1198
1199 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1200 cmd.resp_type = MMC_RSP_R1;
1201 cmd.cmdarg = 0;
1202
1203 timeout = 3;
1204
1205retry_scr:
1206 data.dest = (char *)scr;
1207 data.blocksize = 8;
1208 data.blocks = 1;
1209 data.flags = MMC_DATA_READ;
1210
1211 err = mmc_send_cmd(mmc, &cmd, &data);
1212
1213 if (err) {
1214 if (timeout--)
1215 goto retry_scr;
1216
1217 return err;
1218 }
1219
1220 mmc->scr[0] = __be32_to_cpu(scr[0]);
1221 mmc->scr[1] = __be32_to_cpu(scr[1]);
1222
1223 switch ((mmc->scr[0] >> 24) & 0xf) {
1224 case 0:
1225 mmc->version = SD_VERSION_1_0;
1226 break;
1227 case 1:
1228 mmc->version = SD_VERSION_1_10;
1229 break;
1230 case 2:
1231 mmc->version = SD_VERSION_2;
1232 if ((mmc->scr[0] >> 15) & 0x1)
1233 mmc->version = SD_VERSION_3;
1234 break;
1235 default:
1236 mmc->version = SD_VERSION_1_0;
1237 break;
1238 }
1239
1240 if (mmc->scr[0] & SD_DATA_4BIT)
1241 mmc->card_caps |= MMC_MODE_4BIT;
1242
1243
1244 if (mmc->version == SD_VERSION_1_0)
1245 return 0;
1246
1247 timeout = 4;
1248 while (timeout--) {
1249 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1250 (u8 *)switch_status);
1251
1252 if (err)
1253 return err;
1254
1255
1256 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1257 break;
1258 }
1259
1260
1261 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1262 mmc->card_caps |= MMC_CAP(SD_HS);
1263
1264#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1265
1266 if (mmc->version < SD_VERSION_3)
1267 return 0;
1268
1269 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1270 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1271 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1272 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1273 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1274 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1275 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1276 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1277 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1278 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1279 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1280#endif
1281
1282 return 0;
1283}
1284
1285static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1286{
1287 int err;
1288
1289 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1290 int speed;
1291
1292
1293 if (mmc->version == SD_VERSION_1_0)
1294 return 0;
1295
1296 switch (mode) {
1297 case SD_LEGACY:
1298 speed = UHS_SDR12_BUS_SPEED;
1299 break;
1300 case SD_HS:
1301 speed = HIGH_SPEED_BUS_SPEED;
1302 break;
1303#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1304 case UHS_SDR12:
1305 speed = UHS_SDR12_BUS_SPEED;
1306 break;
1307 case UHS_SDR25:
1308 speed = UHS_SDR25_BUS_SPEED;
1309 break;
1310 case UHS_SDR50:
1311 speed = UHS_SDR50_BUS_SPEED;
1312 break;
1313 case UHS_DDR50:
1314 speed = UHS_DDR50_BUS_SPEED;
1315 break;
1316 case UHS_SDR104:
1317 speed = UHS_SDR104_BUS_SPEED;
1318 break;
1319#endif
1320 default:
1321 return -EINVAL;
1322 }
1323
1324 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1325 if (err)
1326 return err;
1327
1328 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1329 return -ENOTSUPP;
1330
1331 return 0;
1332}
1333
1334static int sd_select_bus_width(struct mmc *mmc, int w)
1335{
1336 int err;
1337 struct mmc_cmd cmd;
1338
1339 if ((w != 4) && (w != 1))
1340 return -EINVAL;
1341
1342 cmd.cmdidx = MMC_CMD_APP_CMD;
1343 cmd.resp_type = MMC_RSP_R1;
1344 cmd.cmdarg = mmc->rca << 16;
1345
1346 err = mmc_send_cmd(mmc, &cmd, NULL);
1347 if (err)
1348 return err;
1349
1350 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1351 cmd.resp_type = MMC_RSP_R1;
1352 if (w == 4)
1353 cmd.cmdarg = 2;
1354 else if (w == 1)
1355 cmd.cmdarg = 0;
1356 err = mmc_send_cmd(mmc, &cmd, NULL);
1357 if (err)
1358 return err;
1359
1360 return 0;
1361}
1362#endif
1363
1364#if CONFIG_IS_ENABLED(MMC_WRITE)
1365static int sd_read_ssr(struct mmc *mmc)
1366{
1367 static const unsigned int sd_au_size[] = {
1368 0, SZ_16K / 512, SZ_32K / 512,
1369 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1370 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1371 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1372 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1373 SZ_64M / 512,
1374 };
1375 int err, i;
1376 struct mmc_cmd cmd;
1377 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1378 struct mmc_data data;
1379 int timeout = 3;
1380 unsigned int au, eo, et, es;
1381
1382 cmd.cmdidx = MMC_CMD_APP_CMD;
1383 cmd.resp_type = MMC_RSP_R1;
1384 cmd.cmdarg = mmc->rca << 16;
1385
1386 err = mmc_send_cmd(mmc, &cmd, NULL);
1387 if (err)
1388 return err;
1389
1390 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1391 cmd.resp_type = MMC_RSP_R1;
1392 cmd.cmdarg = 0;
1393
1394retry_ssr:
1395 data.dest = (char *)ssr;
1396 data.blocksize = 64;
1397 data.blocks = 1;
1398 data.flags = MMC_DATA_READ;
1399
1400 err = mmc_send_cmd(mmc, &cmd, &data);
1401 if (err) {
1402 if (timeout--)
1403 goto retry_ssr;
1404
1405 return err;
1406 }
1407
1408 for (i = 0; i < 16; i++)
1409 ssr[i] = be32_to_cpu(ssr[i]);
1410
1411 au = (ssr[2] >> 12) & 0xF;
1412 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1413 mmc->ssr.au = sd_au_size[au];
1414 es = (ssr[3] >> 24) & 0xFF;
1415 es |= (ssr[2] & 0xFF) << 8;
1416 et = (ssr[3] >> 18) & 0x3F;
1417 if (es && et) {
1418 eo = (ssr[3] >> 16) & 0x3;
1419 mmc->ssr.erase_timeout = (et * 1000) / es;
1420 mmc->ssr.erase_offset = eo * 1000;
1421 }
1422 } else {
1423 pr_debug("Invalid Allocation Unit Size.\n");
1424 }
1425
1426 return 0;
1427}
1428#endif
1429
1430
1431static const int fbase[] = {
1432 10000,
1433 100000,
1434 1000000,
1435 10000000,
1436};
1437
1438
1439
1440
1441static const u8 multipliers[] = {
1442 0,
1443 10,
1444 12,
1445 13,
1446 15,
1447 20,
1448 25,
1449 30,
1450 35,
1451 40,
1452 45,
1453 50,
1454 55,
1455 60,
1456 70,
1457 80,
1458};
1459
1460static inline int bus_width(uint cap)
1461{
1462 if (cap == MMC_MODE_8BIT)
1463 return 8;
1464 if (cap == MMC_MODE_4BIT)
1465 return 4;
1466 if (cap == MMC_MODE_1BIT)
1467 return 1;
1468 pr_warn("invalid bus witdh capability 0x%x\n", cap);
1469 return 0;
1470}
1471
1472#if !CONFIG_IS_ENABLED(DM_MMC)
1473#ifdef MMC_SUPPORTS_TUNING
1474static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1475{
1476 return -ENOTSUPP;
1477}
1478#endif
1479
1480static void mmc_send_init_stream(struct mmc *mmc)
1481{
1482}
1483
1484static int mmc_set_ios(struct mmc *mmc)
1485{
1486 int ret = 0;
1487
1488 if (mmc->cfg->ops->set_ios)
1489 ret = mmc->cfg->ops->set_ios(mmc);
1490
1491 return ret;
1492}
1493#endif
1494
1495int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1496{
1497 if (!disable) {
1498 if (clock > mmc->cfg->f_max)
1499 clock = mmc->cfg->f_max;
1500
1501 if (clock < mmc->cfg->f_min)
1502 clock = mmc->cfg->f_min;
1503 }
1504
1505 mmc->clock = clock;
1506 mmc->clk_disable = disable;
1507
1508 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1509
1510 return mmc_set_ios(mmc);
1511}
1512
1513static int mmc_set_bus_width(struct mmc *mmc, uint width)
1514{
1515 mmc->bus_width = width;
1516
1517 return mmc_set_ios(mmc);
1518}
1519
1520#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1521
1522
1523
1524
1525
1526void mmc_dump_capabilities(const char *text, uint caps)
1527{
1528 enum bus_mode mode;
1529
1530 pr_debug("%s: widths [", text);
1531 if (caps & MMC_MODE_8BIT)
1532 pr_debug("8, ");
1533 if (caps & MMC_MODE_4BIT)
1534 pr_debug("4, ");
1535 if (caps & MMC_MODE_1BIT)
1536 pr_debug("1, ");
1537 pr_debug("\b\b] modes [");
1538 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1539 if (MMC_CAP(mode) & caps)
1540 pr_debug("%s, ", mmc_mode_name(mode));
1541 pr_debug("\b\b]\n");
1542}
1543#endif
1544
1545struct mode_width_tuning {
1546 enum bus_mode mode;
1547 uint widths;
1548#ifdef MMC_SUPPORTS_TUNING
1549 uint tuning;
1550#endif
1551};
1552
1553#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1554int mmc_voltage_to_mv(enum mmc_voltage voltage)
1555{
1556 switch (voltage) {
1557 case MMC_SIGNAL_VOLTAGE_000: return 0;
1558 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1559 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1560 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1561 }
1562 return -EINVAL;
1563}
1564
1565static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1566{
1567 int err;
1568
1569 if (mmc->signal_voltage == signal_voltage)
1570 return 0;
1571
1572 mmc->signal_voltage = signal_voltage;
1573 err = mmc_set_ios(mmc);
1574 if (err)
1575 pr_debug("unable to set voltage (err %d)\n", err);
1576
1577 return err;
1578}
1579#else
1580static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1581{
1582 return 0;
1583}
1584#endif
1585
1586#if !CONFIG_IS_ENABLED(MMC_TINY)
1587static const struct mode_width_tuning sd_modes_by_pref[] = {
1588#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1589#ifdef MMC_SUPPORTS_TUNING
1590 {
1591 .mode = UHS_SDR104,
1592 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1593 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1594 },
1595#endif
1596 {
1597 .mode = UHS_SDR50,
1598 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1599 },
1600 {
1601 .mode = UHS_DDR50,
1602 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1603 },
1604 {
1605 .mode = UHS_SDR25,
1606 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1607 },
1608#endif
1609 {
1610 .mode = SD_HS,
1611 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1612 },
1613#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1614 {
1615 .mode = UHS_SDR12,
1616 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1617 },
1618#endif
1619 {
1620 .mode = SD_LEGACY,
1621 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1622 }
1623};
1624
1625#define for_each_sd_mode_by_pref(caps, mwt) \
1626 for (mwt = sd_modes_by_pref;\
1627 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1628 mwt++) \
1629 if (caps & MMC_CAP(mwt->mode))
1630
1631static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1632{
1633 int err;
1634 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1635 const struct mode_width_tuning *mwt;
1636#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1637 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1638#else
1639 bool uhs_en = false;
1640#endif
1641 uint caps;
1642
1643#ifdef DEBUG
1644 mmc_dump_capabilities("sd card", card_caps);
1645 mmc_dump_capabilities("host", mmc->host_caps);
1646#endif
1647
1648
1649 caps = card_caps & mmc->host_caps;
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1661 if (!uhs_en && !(mmc_host_is_spi(mmc)) &&
1662 mmc->scr[0] & SD_SCR0_SPEC3 &&
1663 (mmc->card_caps & MMC_MODE_MASK) >= MMC_CAP(UHS_SDR50) &&
1664 (mmc->host_caps & MMC_MODE_MASK) >= MMC_CAP(UHS_SDR50)) {
1665 uhs_en = true;
1666 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
1667 if (err)
1668 return err;
1669 }
1670#endif
1671 if (!uhs_en)
1672 caps &= ~UHS_CAPS;
1673
1674 for_each_sd_mode_by_pref(caps, mwt) {
1675 uint *w;
1676
1677 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1678 if (*w & caps & mwt->widths) {
1679 pr_debug("trying mode %s width %d (at %d MHz)\n",
1680 mmc_mode_name(mwt->mode),
1681 bus_width(*w),
1682 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1683
1684
1685 err = sd_select_bus_width(mmc, bus_width(*w));
1686 if (err)
1687 goto error;
1688 mmc_set_bus_width(mmc, bus_width(*w));
1689
1690
1691 err = sd_set_card_speed(mmc, mwt->mode);
1692 if (err)
1693 goto error;
1694
1695
1696 mmc_select_mode(mmc, mwt->mode);
1697 mmc_set_clock(mmc, mmc->tran_speed,
1698 MMC_CLK_ENABLE);
1699
1700#ifdef MMC_SUPPORTS_TUNING
1701
1702 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1703 err = mmc_execute_tuning(mmc,
1704 mwt->tuning);
1705 if (err) {
1706 pr_debug("tuning failed\n");
1707 goto error;
1708 }
1709 }
1710#endif
1711
1712#if CONFIG_IS_ENABLED(MMC_WRITE)
1713 err = sd_read_ssr(mmc);
1714 if (err)
1715 pr_warn("unable to read ssr\n");
1716#endif
1717 if (!err)
1718 return 0;
1719
1720error:
1721
1722 mmc_select_mode(mmc, SD_LEGACY);
1723 mmc_set_clock(mmc, mmc->tran_speed,
1724 MMC_CLK_ENABLE);
1725 }
1726 }
1727 }
1728
1729 pr_err("unable to select a mode\n");
1730 return -ENOTSUPP;
1731}
1732
1733
1734
1735
1736
1737
1738static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1739{
1740 int err;
1741 const u8 *ext_csd = mmc->ext_csd;
1742 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1743
1744 if (mmc->version < MMC_VERSION_4)
1745 return 0;
1746
1747 err = mmc_send_ext_csd(mmc, test_csd);
1748 if (err)
1749 return err;
1750
1751
1752 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1753 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1754 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1755 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1756 ext_csd[EXT_CSD_REV]
1757 == test_csd[EXT_CSD_REV] &&
1758 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1759 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1760 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1761 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1762 return 0;
1763
1764 return -EBADMSG;
1765}
1766
1767#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1768static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1769 uint32_t allowed_mask)
1770{
1771 u32 card_mask = 0;
1772
1773 switch (mode) {
1774 case MMC_HS_400:
1775 case MMC_HS_200:
1776 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1777 EXT_CSD_CARD_TYPE_HS400_1_8V))
1778 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1779 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1780 EXT_CSD_CARD_TYPE_HS400_1_2V))
1781 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1782 break;
1783 case MMC_DDR_52:
1784 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1785 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1786 MMC_SIGNAL_VOLTAGE_180;
1787 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1788 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1789 break;
1790 default:
1791 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1792 break;
1793 }
1794
1795 while (card_mask & allowed_mask) {
1796 enum mmc_voltage best_match;
1797
1798 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1799 if (!mmc_set_signal_voltage(mmc, best_match))
1800 return 0;
1801
1802 allowed_mask &= ~best_match;
1803 }
1804
1805 return -ENOTSUPP;
1806}
1807#else
1808static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1809 uint32_t allowed_mask)
1810{
1811 return 0;
1812}
1813#endif
1814
1815static const struct mode_width_tuning mmc_modes_by_pref[] = {
1816#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1817 {
1818 .mode = MMC_HS_400,
1819 .widths = MMC_MODE_8BIT,
1820 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1821 },
1822#endif
1823#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1824 {
1825 .mode = MMC_HS_200,
1826 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1827 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1828 },
1829#endif
1830 {
1831 .mode = MMC_DDR_52,
1832 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1833 },
1834 {
1835 .mode = MMC_HS_52,
1836 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1837 },
1838 {
1839 .mode = MMC_HS,
1840 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1841 },
1842 {
1843 .mode = MMC_LEGACY,
1844 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1845 }
1846};
1847
1848#define for_each_mmc_mode_by_pref(caps, mwt) \
1849 for (mwt = mmc_modes_by_pref;\
1850 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1851 mwt++) \
1852 if (caps & MMC_CAP(mwt->mode))
1853
1854static const struct ext_csd_bus_width {
1855 uint cap;
1856 bool is_ddr;
1857 uint ext_csd_bits;
1858} ext_csd_bus_width[] = {
1859 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1860 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1861 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1862 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1863 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1864};
1865
1866#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1867static int mmc_select_hs400(struct mmc *mmc)
1868{
1869 int err;
1870
1871
1872 err = mmc_set_card_speed(mmc, MMC_HS_200);
1873 if (err)
1874 return err;
1875
1876
1877 mmc_select_mode(mmc, MMC_HS_200);
1878 mmc_set_clock(mmc, mmc->tran_speed, false);
1879
1880
1881 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1882 if (err) {
1883 debug("tuning failed\n");
1884 return err;
1885 }
1886
1887
1888 mmc_set_card_speed(mmc, MMC_HS);
1889 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
1890
1891 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1892 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1893 if (err)
1894 return err;
1895
1896 err = mmc_set_card_speed(mmc, MMC_HS_400);
1897 if (err)
1898 return err;
1899
1900 mmc_select_mode(mmc, MMC_HS_400);
1901 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1902 if (err)
1903 return err;
1904
1905 return 0;
1906}
1907#else
1908static int mmc_select_hs400(struct mmc *mmc)
1909{
1910 return -ENOTSUPP;
1911}
1912#endif
1913
1914#define for_each_supported_width(caps, ddr, ecbv) \
1915 for (ecbv = ext_csd_bus_width;\
1916 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1917 ecbv++) \
1918 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1919
1920static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1921{
1922 int err;
1923 const struct mode_width_tuning *mwt;
1924 const struct ext_csd_bus_width *ecbw;
1925
1926#ifdef DEBUG
1927 mmc_dump_capabilities("mmc", card_caps);
1928 mmc_dump_capabilities("host", mmc->host_caps);
1929#endif
1930
1931
1932 card_caps &= mmc->host_caps;
1933
1934
1935 if (mmc->version < MMC_VERSION_4)
1936 return 0;
1937
1938 if (!mmc->ext_csd) {
1939 pr_debug("No ext_csd found!\n");
1940 return -ENOTSUPP;
1941 }
1942
1943 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
1944
1945 for_each_mmc_mode_by_pref(card_caps, mwt) {
1946 for_each_supported_width(card_caps & mwt->widths,
1947 mmc_is_mode_ddr(mwt->mode), ecbw) {
1948 enum mmc_voltage old_voltage;
1949 pr_debug("trying mode %s width %d (at %d MHz)\n",
1950 mmc_mode_name(mwt->mode),
1951 bus_width(ecbw->cap),
1952 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1953 old_voltage = mmc->signal_voltage;
1954 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1955 MMC_ALL_SIGNAL_VOLTAGE);
1956 if (err)
1957 continue;
1958
1959
1960 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1961 EXT_CSD_BUS_WIDTH,
1962 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1963 if (err)
1964 goto error;
1965 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1966
1967 if (mwt->mode == MMC_HS_400) {
1968 err = mmc_select_hs400(mmc);
1969 if (err) {
1970 printf("Select HS400 failed %d\n", err);
1971 goto error;
1972 }
1973 } else {
1974
1975 err = mmc_set_card_speed(mmc, mwt->mode);
1976 if (err)
1977 goto error;
1978
1979
1980
1981
1982
1983
1984 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1985 err = mmc_switch(mmc,
1986 EXT_CSD_CMD_SET_NORMAL,
1987 EXT_CSD_BUS_WIDTH,
1988 ecbw->ext_csd_bits);
1989 if (err)
1990 goto error;
1991 }
1992
1993
1994 mmc_select_mode(mmc, mwt->mode);
1995 mmc_set_clock(mmc, mmc->tran_speed,
1996 MMC_CLK_ENABLE);
1997#ifdef MMC_SUPPORTS_TUNING
1998
1999
2000 if (mwt->tuning) {
2001 err = mmc_execute_tuning(mmc,
2002 mwt->tuning);
2003 if (err) {
2004 pr_debug("tuning failed\n");
2005 goto error;
2006 }
2007 }
2008#endif
2009 }
2010
2011
2012 err = mmc_read_and_compare_ext_csd(mmc);
2013 if (!err)
2014 return 0;
2015error:
2016 mmc_set_signal_voltage(mmc, old_voltage);
2017
2018 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2019 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2020 mmc_select_mode(mmc, MMC_LEGACY);
2021 mmc_set_bus_width(mmc, 1);
2022 }
2023 }
2024
2025 pr_err("unable to select a mode\n");
2026
2027 return -ENOTSUPP;
2028}
2029#endif
2030
2031#if CONFIG_IS_ENABLED(MMC_TINY)
2032DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2033#endif
2034
2035static int mmc_startup_v4(struct mmc *mmc)
2036{
2037 int err, i;
2038 u64 capacity;
2039 bool has_parts = false;
2040 bool part_completed;
2041 static const u32 mmc_versions[] = {
2042 MMC_VERSION_4,
2043 MMC_VERSION_4_1,
2044 MMC_VERSION_4_2,
2045 MMC_VERSION_4_3,
2046 MMC_VERSION_4_4,
2047 MMC_VERSION_4_41,
2048 MMC_VERSION_4_5,
2049 MMC_VERSION_5_0,
2050 MMC_VERSION_5_1
2051 };
2052
2053#if CONFIG_IS_ENABLED(MMC_TINY)
2054 u8 *ext_csd = ext_csd_bkup;
2055
2056 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2057 return 0;
2058
2059 if (!mmc->ext_csd)
2060 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2061
2062 err = mmc_send_ext_csd(mmc, ext_csd);
2063 if (err)
2064 goto error;
2065
2066
2067 if (!mmc->ext_csd)
2068 mmc->ext_csd = ext_csd;
2069#else
2070 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2071
2072 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2073 return 0;
2074
2075
2076 err = mmc_send_ext_csd(mmc, ext_csd);
2077 if (err)
2078 goto error;
2079
2080
2081 if (!mmc->ext_csd)
2082 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2083 if (!mmc->ext_csd)
2084 return -ENOMEM;
2085 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2086#endif
2087 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2088 return -EINVAL;
2089
2090 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2091
2092 if (mmc->version >= MMC_VERSION_4_2) {
2093
2094
2095
2096
2097
2098 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2099 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2100 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2101 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2102 capacity *= MMC_MAX_BLOCK_LEN;
2103 if ((capacity >> 20) > 2 * 1024)
2104 mmc->capacity_user = capacity;
2105 }
2106
2107
2108
2109
2110
2111
2112
2113 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2114 EXT_CSD_PARTITION_SETTING_COMPLETED);
2115
2116
2117 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2118 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2119 ext_csd[EXT_CSD_BOOT_MULT])
2120 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2121 if (part_completed &&
2122 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2123 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2124
2125 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2126
2127 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2128
2129 for (i = 0; i < 4; i++) {
2130 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2131 uint mult = (ext_csd[idx + 2] << 16) +
2132 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2133 if (mult)
2134 has_parts = true;
2135 if (!part_completed)
2136 continue;
2137 mmc->capacity_gp[i] = mult;
2138 mmc->capacity_gp[i] *=
2139 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2140 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2141 mmc->capacity_gp[i] <<= 19;
2142 }
2143
2144#ifndef CONFIG_SPL_BUILD
2145 if (part_completed) {
2146 mmc->enh_user_size =
2147 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2148 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2149 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2150 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2151 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2152 mmc->enh_user_size <<= 19;
2153 mmc->enh_user_start =
2154 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2155 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2156 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2157 ext_csd[EXT_CSD_ENH_START_ADDR];
2158 if (mmc->high_capacity)
2159 mmc->enh_user_start <<= 9;
2160 }
2161#endif
2162
2163
2164
2165
2166
2167
2168 if (part_completed)
2169 has_parts = true;
2170 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2171 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2172 has_parts = true;
2173 if (has_parts) {
2174 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2175 EXT_CSD_ERASE_GROUP_DEF, 1);
2176
2177 if (err)
2178 goto error;
2179
2180 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2181 }
2182
2183 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2184#if CONFIG_IS_ENABLED(MMC_WRITE)
2185
2186 mmc->erase_grp_size =
2187 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2188#endif
2189
2190
2191
2192
2193
2194 if (mmc->high_capacity && part_completed) {
2195 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2196 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2197 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2198 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2199 capacity *= MMC_MAX_BLOCK_LEN;
2200 mmc->capacity_user = capacity;
2201 }
2202 }
2203#if CONFIG_IS_ENABLED(MMC_WRITE)
2204 else {
2205
2206 int erase_gsz, erase_gmul;
2207
2208 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2209 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2210 mmc->erase_grp_size = (erase_gsz + 1)
2211 * (erase_gmul + 1);
2212 }
2213#endif
2214#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2215 mmc->hc_wp_grp_size = 1024
2216 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2217 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2218#endif
2219
2220 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2221
2222 return 0;
2223error:
2224 if (mmc->ext_csd) {
2225#if !CONFIG_IS_ENABLED(MMC_TINY)
2226 free(mmc->ext_csd);
2227#endif
2228 mmc->ext_csd = NULL;
2229 }
2230 return err;
2231}
2232
2233static int mmc_startup(struct mmc *mmc)
2234{
2235 int err, i;
2236 uint mult, freq;
2237 u64 cmult, csize;
2238 struct mmc_cmd cmd;
2239 struct blk_desc *bdesc;
2240
2241#ifdef CONFIG_MMC_SPI_CRC_ON
2242 if (mmc_host_is_spi(mmc)) {
2243 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2244 cmd.resp_type = MMC_RSP_R1;
2245 cmd.cmdarg = 1;
2246 err = mmc_send_cmd(mmc, &cmd, NULL);
2247 if (err)
2248 return err;
2249 }
2250#endif
2251
2252
2253 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2254 MMC_CMD_ALL_SEND_CID;
2255 cmd.resp_type = MMC_RSP_R2;
2256 cmd.cmdarg = 0;
2257
2258 err = mmc_send_cmd(mmc, &cmd, NULL);
2259
2260#ifdef CONFIG_MMC_QUIRKS
2261 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2262 int retries = 4;
2263
2264
2265
2266
2267 do {
2268 err = mmc_send_cmd(mmc, &cmd, NULL);
2269 if (!err)
2270 break;
2271 } while (retries--);
2272 }
2273#endif
2274
2275 if (err)
2276 return err;
2277
2278 memcpy(mmc->cid, cmd.response, 16);
2279
2280
2281
2282
2283
2284
2285 if (!mmc_host_is_spi(mmc)) {
2286 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2287 cmd.cmdarg = mmc->rca << 16;
2288 cmd.resp_type = MMC_RSP_R6;
2289
2290 err = mmc_send_cmd(mmc, &cmd, NULL);
2291
2292 if (err)
2293 return err;
2294
2295 if (IS_SD(mmc))
2296 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2297 }
2298
2299
2300 cmd.cmdidx = MMC_CMD_SEND_CSD;
2301 cmd.resp_type = MMC_RSP_R2;
2302 cmd.cmdarg = mmc->rca << 16;
2303
2304 err = mmc_send_cmd(mmc, &cmd, NULL);
2305
2306 if (err)
2307 return err;
2308
2309 mmc->csd[0] = cmd.response[0];
2310 mmc->csd[1] = cmd.response[1];
2311 mmc->csd[2] = cmd.response[2];
2312 mmc->csd[3] = cmd.response[3];
2313
2314 if (mmc->version == MMC_VERSION_UNKNOWN) {
2315 int version = (cmd.response[0] >> 26) & 0xf;
2316
2317 switch (version) {
2318 case 0:
2319 mmc->version = MMC_VERSION_1_2;
2320 break;
2321 case 1:
2322 mmc->version = MMC_VERSION_1_4;
2323 break;
2324 case 2:
2325 mmc->version = MMC_VERSION_2_2;
2326 break;
2327 case 3:
2328 mmc->version = MMC_VERSION_3;
2329 break;
2330 case 4:
2331 mmc->version = MMC_VERSION_4;
2332 break;
2333 default:
2334 mmc->version = MMC_VERSION_1_2;
2335 break;
2336 }
2337 }
2338
2339
2340 freq = fbase[(cmd.response[0] & 0x7)];
2341 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2342
2343 mmc->legacy_speed = freq * mult;
2344 mmc_select_mode(mmc, MMC_LEGACY);
2345
2346 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2347 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2348#if CONFIG_IS_ENABLED(MMC_WRITE)
2349
2350 if (IS_SD(mmc))
2351 mmc->write_bl_len = mmc->read_bl_len;
2352 else
2353 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2354#endif
2355
2356 if (mmc->high_capacity) {
2357 csize = (mmc->csd[1] & 0x3f) << 16
2358 | (mmc->csd[2] & 0xffff0000) >> 16;
2359 cmult = 8;
2360 } else {
2361 csize = (mmc->csd[1] & 0x3ff) << 2
2362 | (mmc->csd[2] & 0xc0000000) >> 30;
2363 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2364 }
2365
2366 mmc->capacity_user = (csize + 1) << (cmult + 2);
2367 mmc->capacity_user *= mmc->read_bl_len;
2368 mmc->capacity_boot = 0;
2369 mmc->capacity_rpmb = 0;
2370 for (i = 0; i < 4; i++)
2371 mmc->capacity_gp[i] = 0;
2372
2373 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2374 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2375
2376#if CONFIG_IS_ENABLED(MMC_WRITE)
2377 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2378 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2379#endif
2380
2381 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2382 cmd.cmdidx = MMC_CMD_SET_DSR;
2383 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2384 cmd.resp_type = MMC_RSP_NONE;
2385 if (mmc_send_cmd(mmc, &cmd, NULL))
2386 pr_warn("MMC: SET_DSR failed\n");
2387 }
2388
2389
2390 if (!mmc_host_is_spi(mmc)) {
2391 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2392 cmd.resp_type = MMC_RSP_R1;
2393 cmd.cmdarg = mmc->rca << 16;
2394 err = mmc_send_cmd(mmc, &cmd, NULL);
2395
2396 if (err)
2397 return err;
2398 }
2399
2400
2401
2402
2403#if CONFIG_IS_ENABLED(MMC_WRITE)
2404 mmc->erase_grp_size = 1;
2405#endif
2406 mmc->part_config = MMCPART_NOAVAILABLE;
2407
2408 err = mmc_startup_v4(mmc);
2409 if (err)
2410 return err;
2411
2412 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2413 if (err)
2414 return err;
2415
2416#if CONFIG_IS_ENABLED(MMC_TINY)
2417 mmc_set_clock(mmc, mmc->legacy_speed, false);
2418 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2419 mmc_set_bus_width(mmc, 1);
2420#else
2421 if (IS_SD(mmc)) {
2422 err = sd_get_capabilities(mmc);
2423 if (err)
2424 return err;
2425 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2426 } else {
2427 err = mmc_get_capabilities(mmc);
2428 if (err)
2429 return err;
2430 mmc_select_mode_and_width(mmc, mmc->card_caps);
2431 }
2432#endif
2433 if (err)
2434 return err;
2435
2436 mmc->best_mode = mmc->selected_mode;
2437
2438
2439 if (mmc->ddr_mode) {
2440 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2441#if CONFIG_IS_ENABLED(MMC_WRITE)
2442 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2443#endif
2444 }
2445
2446
2447 bdesc = mmc_get_blk_desc(mmc);
2448 bdesc->lun = 0;
2449 bdesc->hwpart = 0;
2450 bdesc->type = 0;
2451 bdesc->blksz = mmc->read_bl_len;
2452 bdesc->log2blksz = LOG2(bdesc->blksz);
2453 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2454#if !defined(CONFIG_SPL_BUILD) || \
2455 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2456 !defined(CONFIG_USE_TINY_PRINTF))
2457 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2458 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2459 (mmc->cid[3] >> 16) & 0xffff);
2460 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2461 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2462 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2463 (mmc->cid[2] >> 24) & 0xff);
2464 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2465 (mmc->cid[2] >> 16) & 0xf);
2466#else
2467 bdesc->vendor[0] = 0;
2468 bdesc->product[0] = 0;
2469 bdesc->revision[0] = 0;
2470#endif
2471
2472#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2473 part_init(bdesc);
2474#endif
2475
2476 return 0;
2477}
2478
2479static int mmc_send_if_cond(struct mmc *mmc)
2480{
2481 struct mmc_cmd cmd;
2482 int err;
2483
2484 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2485
2486 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2487 cmd.resp_type = MMC_RSP_R7;
2488
2489 err = mmc_send_cmd(mmc, &cmd, NULL);
2490
2491 if (err)
2492 return err;
2493
2494 if ((cmd.response[0] & 0xff) != 0xaa)
2495 return -EOPNOTSUPP;
2496 else
2497 mmc->version = SD_VERSION_2;
2498
2499 return 0;
2500}
2501
2502#if !CONFIG_IS_ENABLED(DM_MMC)
2503
2504__weak void board_mmc_power_init(void)
2505{
2506}
2507#endif
2508
2509static int mmc_power_init(struct mmc *mmc)
2510{
2511#if CONFIG_IS_ENABLED(DM_MMC)
2512#if CONFIG_IS_ENABLED(DM_REGULATOR)
2513 int ret;
2514
2515 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2516 &mmc->vmmc_supply);
2517 if (ret)
2518 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2519
2520 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2521 &mmc->vqmmc_supply);
2522 if (ret)
2523 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2524#endif
2525#else
2526
2527
2528
2529
2530 board_mmc_power_init();
2531#endif
2532 return 0;
2533}
2534
2535
2536
2537
2538
2539
2540static void mmc_set_initial_state(struct mmc *mmc)
2541{
2542 int err;
2543
2544
2545 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2546 if (err != 0)
2547 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2548 if (err != 0)
2549 pr_warn("mmc: failed to set signal voltage\n");
2550
2551 mmc_select_mode(mmc, MMC_LEGACY);
2552 mmc_set_bus_width(mmc, 1);
2553 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2554}
2555
2556static int mmc_power_on(struct mmc *mmc)
2557{
2558#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2559 if (mmc->vmmc_supply) {
2560 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2561
2562 if (ret) {
2563 puts("Error enabling VMMC supply\n");
2564 return ret;
2565 }
2566 }
2567#endif
2568 return 0;
2569}
2570
2571static int mmc_power_off(struct mmc *mmc)
2572{
2573 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2574#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2575 if (mmc->vmmc_supply) {
2576 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2577
2578 if (ret) {
2579 pr_debug("Error disabling VMMC supply\n");
2580 return ret;
2581 }
2582 }
2583#endif
2584 return 0;
2585}
2586
2587static int mmc_power_cycle(struct mmc *mmc)
2588{
2589 int ret;
2590
2591 ret = mmc_power_off(mmc);
2592 if (ret)
2593 return ret;
2594
2595
2596
2597
2598 udelay(2000);
2599 return mmc_power_on(mmc);
2600}
2601
2602int mmc_get_op_cond(struct mmc *mmc)
2603{
2604 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2605 int err;
2606
2607 if (mmc->has_init)
2608 return 0;
2609
2610#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2611 mmc_adapter_card_type_ident();
2612#endif
2613 err = mmc_power_init(mmc);
2614 if (err)
2615 return err;
2616
2617#ifdef CONFIG_MMC_QUIRKS
2618 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2619 MMC_QUIRK_RETRY_SEND_CID;
2620#endif
2621
2622 err = mmc_power_cycle(mmc);
2623 if (err) {
2624
2625
2626
2627
2628
2629 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2630 uhs_en = false;
2631 mmc->host_caps &= ~UHS_CAPS;
2632 err = mmc_power_on(mmc);
2633 }
2634 if (err)
2635 return err;
2636
2637#if CONFIG_IS_ENABLED(DM_MMC)
2638
2639#else
2640
2641 err = mmc->cfg->ops->init(mmc);
2642 if (err)
2643 return err;
2644#endif
2645 mmc->ddr_mode = 0;
2646
2647retry:
2648 mmc_set_initial_state(mmc);
2649 mmc_send_init_stream(mmc);
2650
2651
2652 err = mmc_go_idle(mmc);
2653
2654 if (err)
2655 return err;
2656
2657
2658 mmc_get_blk_desc(mmc)->hwpart = 0;
2659
2660
2661 err = mmc_send_if_cond(mmc);
2662
2663
2664 err = sd_send_op_cond(mmc, uhs_en);
2665 if (err && uhs_en) {
2666 uhs_en = false;
2667 mmc_power_cycle(mmc);
2668 goto retry;
2669 }
2670
2671
2672 if (err == -ETIMEDOUT) {
2673 err = mmc_send_op_cond(mmc);
2674
2675 if (err) {
2676#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2677 pr_err("Card did not respond to voltage select!\n");
2678#endif
2679 return -EOPNOTSUPP;
2680 }
2681 }
2682
2683 return err;
2684}
2685
2686int mmc_start_init(struct mmc *mmc)
2687{
2688 bool no_card;
2689 int err = 0;
2690
2691
2692
2693
2694
2695 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2696 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2697
2698#if !defined(CONFIG_MMC_BROKEN_CD)
2699
2700 no_card = mmc_getcd(mmc) == 0;
2701#else
2702 no_card = 0;
2703#endif
2704#if !CONFIG_IS_ENABLED(DM_MMC)
2705 no_card = no_card || (mmc->cfg->ops->init == NULL);
2706#endif
2707 if (no_card) {
2708 mmc->has_init = 0;
2709#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2710 pr_err("MMC: no card present\n");
2711#endif
2712 return -ENOMEDIUM;
2713 }
2714
2715 err = mmc_get_op_cond(mmc);
2716
2717 if (!err)
2718 mmc->init_in_progress = 1;
2719
2720 return err;
2721}
2722
2723static int mmc_complete_init(struct mmc *mmc)
2724{
2725 int err = 0;
2726
2727 mmc->init_in_progress = 0;
2728 if (mmc->op_cond_pending)
2729 err = mmc_complete_op_cond(mmc);
2730
2731 if (!err)
2732 err = mmc_startup(mmc);
2733 if (err)
2734 mmc->has_init = 0;
2735 else
2736 mmc->has_init = 1;
2737 return err;
2738}
2739
2740int mmc_init(struct mmc *mmc)
2741{
2742 int err = 0;
2743 __maybe_unused ulong start;
2744#if CONFIG_IS_ENABLED(DM_MMC)
2745 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2746
2747 upriv->mmc = mmc;
2748#endif
2749 if (mmc->has_init)
2750 return 0;
2751
2752 start = get_timer(0);
2753
2754 if (!mmc->init_in_progress)
2755 err = mmc_start_init(mmc);
2756
2757 if (!err)
2758 err = mmc_complete_init(mmc);
2759 if (err)
2760 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2761
2762 return err;
2763}
2764
2765int mmc_set_dsr(struct mmc *mmc, u16 val)
2766{
2767 mmc->dsr = val;
2768 return 0;
2769}
2770
2771
2772__weak int cpu_mmc_init(bd_t *bis)
2773{
2774 return -1;
2775}
2776
2777
2778__weak int board_mmc_init(bd_t *bis)
2779{
2780 return -1;
2781}
2782
2783void mmc_set_preinit(struct mmc *mmc, int preinit)
2784{
2785 mmc->preinit = preinit;
2786}
2787
2788#if CONFIG_IS_ENABLED(DM_MMC)
2789static int mmc_probe(bd_t *bis)
2790{
2791 int ret, i;
2792 struct uclass *uc;
2793 struct udevice *dev;
2794
2795 ret = uclass_get(UCLASS_MMC, &uc);
2796 if (ret)
2797 return ret;
2798
2799
2800
2801
2802
2803
2804 for (i = 0; ; i++) {
2805 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2806 if (ret == -ENODEV)
2807 break;
2808 }
2809 uclass_foreach_dev(dev, uc) {
2810 ret = device_probe(dev);
2811 if (ret)
2812 pr_err("%s - probe failed: %d\n", dev->name, ret);
2813 }
2814
2815 return 0;
2816}
2817#else
2818static int mmc_probe(bd_t *bis)
2819{
2820 if (board_mmc_init(bis) < 0)
2821 cpu_mmc_init(bis);
2822
2823 return 0;
2824}
2825#endif
2826
2827int mmc_initialize(bd_t *bis)
2828{
2829 static int initialized = 0;
2830 int ret;
2831 if (initialized)
2832 return 0;
2833 initialized = 1;
2834
2835#if !CONFIG_IS_ENABLED(BLK)
2836#if !CONFIG_IS_ENABLED(MMC_TINY)
2837 mmc_list_init();
2838#endif
2839#endif
2840 ret = mmc_probe(bis);
2841 if (ret)
2842 return ret;
2843
2844#ifndef CONFIG_SPL_BUILD
2845 print_mmc_devices(',');
2846#endif
2847
2848 mmc_do_preinit();
2849 return 0;
2850}
2851
2852#ifdef CONFIG_CMD_BKOPS_ENABLE
2853int mmc_set_bkops_enable(struct mmc *mmc)
2854{
2855 int err;
2856 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2857
2858 err = mmc_send_ext_csd(mmc, ext_csd);
2859 if (err) {
2860 puts("Could not get ext_csd register values\n");
2861 return err;
2862 }
2863
2864 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2865 puts("Background operations not supported on device\n");
2866 return -EMEDIUMTYPE;
2867 }
2868
2869 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2870 puts("Background operations already enabled\n");
2871 return 0;
2872 }
2873
2874 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2875 if (err) {
2876 puts("Failed to enable manual background operations\n");
2877 return err;
2878 }
2879
2880 puts("Enabled manual background operations\n");
2881
2882 return 0;
2883}
2884#endif
2885
