LXR uboot/drivers/net/fsl

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2000-2004
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
   7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8 */
   9
  10#include <common.h>
  11#include <environment.h>
  12#include <malloc.h>
  13#include <command.h>
  14#include <config.h>
  15#include <net.h>
  16#include <miiphy.h>
  17
  18#undef  ET_DEBUG
  19#undef  MII_DEBUG
  20
  21/* Ethernet Transmit and Receive Buffers */
  22#define DBUF_LENGTH             1520
  23#define PKT_MAXBUF_SIZE         1518
  24#define PKT_MINBUF_SIZE         64
  25#define PKT_MAXBLR_SIZE         1536
  26#define LAST_PKTBUFSRX          PKTBUFSRX - 1
  27#define BD_ENET_RX_W_E          (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
  28#define BD_ENET_TX_RDY_LST      (BD_ENET_TX_READY | BD_ENET_TX_LAST)
  29#define FIFO_ERRSTAT            (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
  30
  31/* RxBD bits definitions */
  32#define BD_ENET_RX_ERR  (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
  33                         BD_ENET_RX_OV | BD_ENET_RX_TR)
  34
  35#include <asm/immap.h>
  36#include <asm/fsl_mcdmafec.h>
  37
  38#include "MCD_dma.h"
  39
  40struct fec_info_dma fec_info[] = {
  41#ifdef CONFIG_SYS_FEC0_IOBASE
  42        {
  43         0,                     /* index */
  44         CONFIG_SYS_FEC0_IOBASE,        /* io base */
  45         CONFIG_SYS_FEC0_PINMUX,        /* gpio pin muxing */
  46         CONFIG_SYS_FEC0_MIIBASE,       /* mii base */
  47         -1,                    /* phy_addr */
  48         0,                     /* duplex and speed */
  49         0,                     /* phy name */
  50         0,                     /* phyname init */
  51         0,                     /* RX BD */
  52         0,                     /* TX BD */
  53         0,                     /* rx Index */
  54         0,                     /* tx Index */
  55         0,                     /* tx buffer */
  56         0,                     /* initialized flag */
  57         (struct fec_info_dma *)-1,     /* next */
  58         FEC0_RX_TASK,          /* rxTask */
  59         FEC0_TX_TASK,          /* txTask */
  60         FEC0_RX_PRIORITY,      /* rxPri */
  61         FEC0_TX_PRIORITY,      /* txPri */
  62         FEC0_RX_INIT,          /* rxInit */
  63         FEC0_TX_INIT,          /* txInit */
  64         0,                     /* usedTbdIndex */
  65         0,                     /* cleanTbdNum */
  66         },
  67#endif
  68#ifdef CONFIG_SYS_FEC1_IOBASE
  69        {
  70         1,                     /* index */
  71         CONFIG_SYS_FEC1_IOBASE,        /* io base */
  72         CONFIG_SYS_FEC1_PINMUX,        /* gpio pin muxing */
  73         CONFIG_SYS_FEC1_MIIBASE,       /* mii base */
  74         -1,                    /* phy_addr */
  75         0,                     /* duplex and speed */
  76         0,                     /* phy name */
  77         0,                     /* phy name init */
  78#ifdef CONFIG_SYS_DMA_USE_INTSRAM
  79         (cbd_t *)DBUF_LENGTH,  /* RX BD */
  80#else
  81         0,                     /* RX BD */
  82#endif
  83         0,                     /* TX BD */
  84         0,                     /* rx Index */
  85         0,                     /* tx Index */
  86         0,                     /* tx buffer */
  87         0,                     /* initialized flag */
  88         (struct fec_info_dma *)-1,     /* next */
  89         FEC1_RX_TASK,          /* rxTask */
  90         FEC1_TX_TASK,          /* txTask */
  91         FEC1_RX_PRIORITY,      /* rxPri */
  92         FEC1_TX_PRIORITY,      /* txPri */
  93         FEC1_RX_INIT,          /* rxInit */
  94         FEC1_TX_INIT,          /* txInit */
  95         0,                     /* usedTbdIndex */
  96         0,                     /* cleanTbdNum */
  97         }
  98#endif
  99};
 100
 101static int fec_send(struct eth_device *dev, void *packet, int length);
 102static int fec_recv(struct eth_device *dev);
 103static int fec_init(struct eth_device *dev, bd_t * bd);
 104static void fec_halt(struct eth_device *dev);
 105
 106#ifdef ET_DEBUG
 107static void dbg_fec_regs(struct eth_device *dev)
 108{
 109        struct fec_info_dma *info = dev->priv;
 110        volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
 111
 112        printf("=====\n");
 113        printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
 114        printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
 115        printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
 116        printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
 117        printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
 118        printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
 119        printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
 120        printf("r hash       %x - %x\n", (int)&fecp->rhr, fecp->rhr);
 121        printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
 122        printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
 123        printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
 124        printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
 125        printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
 126        printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
 127        printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
 128        printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
 129        printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
 130        printf("r_fdata      %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
 131        printf("r_fstat      %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
 132        printf("r_fctrl      %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
 133        printf("r_flrfp      %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
 134        printf("r_flwfp      %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
 135        printf("r_frfar      %x - %x\n", (int)&fecp->rfar, fecp->rfar);
 136        printf("r_frfrp      %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
 137        printf("r_frfwp      %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
 138        printf("t_fdata      %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
 139        printf("t_fstat      %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
 140        printf("t_fctrl      %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
 141        printf("t_flrfp      %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
 142        printf("t_flwfp      %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
 143        printf("t_ftfar      %x - %x\n", (int)&fecp->tfar, fecp->tfar);
 144        printf("t_ftfrp      %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
 145        printf("t_ftfwp      %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
 146        printf("frst         %x - %x\n", (int)&fecp->frst, fecp->frst);
 147        printf("ctcwr        %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
 148}
 149#endif
 150
 151static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
 152                                 int dup_spd)
 153{
 154        if ((dup_spd >> 16) == FULL) {
 155                /* Set maximum frame length */
 156                fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
 157                    FEC_RCR_PROM | 0x100;
 158                fecp->tcr = FEC_TCR_FDEN;
 159        } else {
 160                /* Half duplex mode */
 161                fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
 162                    FEC_RCR_MII_MODE | FEC_RCR_DRT;
 163                fecp->tcr &= ~FEC_TCR_FDEN;
 164        }
 165
 166        if ((dup_spd & 0xFFFF) == _100BASET) {
 167#ifdef MII_DEBUG
 168                printf("100Mbps\n");
 169#endif
 170                bd->bi_ethspeed = 100;
 171        } else {
 172#ifdef MII_DEBUG
 173                printf("10Mbps\n");
 174#endif
 175                bd->bi_ethspeed = 10;
 176        }
 177}
 178
 179static int fec_send(struct eth_device *dev, void *packet, int length)
 180{
 181        struct fec_info_dma *info = dev->priv;
 182        cbd_t *pTbd, *pUsedTbd;
 183        u16 phyStatus;
 184
 185        miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
 186
 187        /* process all the consumed TBDs */
 188        while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
 189                pUsedTbd = &info->txbd[info->usedTbdIdx];
 190                if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
 191#ifdef ET_DEBUG
 192                        printf("Cannot clean TBD %d, in use\n",
 193                               info->cleanTbdNum);
 194#endif
 195                        return 0;
 196                }
 197
 198                /* clean this buffer descriptor */
 199                if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
 200                        pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
 201                else
 202                        pUsedTbd->cbd_sc = 0;
 203
 204                /* update some indeces for a correct handling of the TBD ring */
 205                info->cleanTbdNum++;
 206                info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
 207        }
 208
 209        /* Check for valid length of data. */
 210        if ((length > 1500) || (length <= 0)) {
 211                return -1;
 212        }
 213
 214        /* Check the number of vacant TxBDs. */
 215        if (info->cleanTbdNum < 1) {
 216                printf("No available TxBDs ...\n");
 217                return -1;
 218        }
 219
 220        /* Get the first TxBD to send the mac header */
 221        pTbd = &info->txbd[info->txIdx];
 222        pTbd->cbd_datlen = length;
 223        pTbd->cbd_bufaddr = (u32) packet;
 224        pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
 225        info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
 226
 227        /* Enable DMA transmit task */
 228        MCD_continDma(info->txTask);
 229
 230        info->cleanTbdNum -= 1;
 231
 232        /* wait until frame is sent . */
 233        while (pTbd->cbd_sc & BD_ENET_TX_READY) {
 234                udelay(10);
 235        }
 236
 237        return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
 238}
 239
 240static int fec_recv(struct eth_device *dev)
 241{
 242        struct fec_info_dma *info = dev->priv;
 243        volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
 244
 245        cbd_t *prbd = &info->rxbd[info->rxIdx];
 246        u32 ievent;
 247        int frame_length, len = 0;
 248
 249        /* Check if any critical events have happened */
 250        ievent = fecp->eir;
 251        if (ievent != 0) {
 252                fecp->eir = ievent;
 253
 254                if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
 255                        printf("fec_recv: error\n");
 256                        fec_halt(dev);
 257                        fec_init(dev, NULL);
 258                        return 0;
 259                }
 260
 261                if (ievent & FEC_EIR_HBERR) {
 262                        /* Heartbeat error */
 263                        fecp->tcr |= FEC_TCR_GTS;
 264                }
 265
 266                if (ievent & FEC_EIR_GRA) {
 267                        /* Graceful stop complete */
 268                        if (fecp->tcr & FEC_TCR_GTS) {
 269                                printf("fec_recv: tcr_gts\n");
 270                                fec_halt(dev);
 271                                fecp->tcr &= ~FEC_TCR_GTS;
 272                                fec_init(dev, NULL);
 273                        }
 274                }
 275        }
 276
 277        if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
 278                if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
 279                    !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
 280                    ((prbd->cbd_datlen - 4) > 14)) {
 281
 282                        /* Get buffer address and size */
 283                        frame_length = prbd->cbd_datlen - 4;
 284
 285                        /* Fill the buffer and pass it to upper layers */
 286                        net_process_received_packet((uchar *)prbd->cbd_bufaddr,
 287                                                    frame_length);
 288                        len = frame_length;
 289                }
 290
 291                /* Reset buffer descriptor as empty */
 292                if ((info->rxIdx) == (PKTBUFSRX - 1))
 293                        prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 294                else
 295                        prbd->cbd_sc = BD_ENET_RX_EMPTY;
 296
 297                prbd->cbd_datlen = PKTSIZE_ALIGN;
 298
 299                /* Now, we have an empty RxBD, restart the DMA receive task */
 300                MCD_continDma(info->rxTask);
 301
 302                /* Increment BD count */
 303                info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
 304        }
 305
 306        return len;
 307}
 308
 309static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
 310{
 311        u8 currByte;            /* byte for which to compute the CRC */
 312        int byte;               /* loop - counter */
 313        int bit;                /* loop - counter */
 314        u32 crc = 0xffffffff;   /* initial value */
 315
 316        for (byte = 0; byte < 6; byte++) {
 317                currByte = mac[byte];
 318                for (bit = 0; bit < 8; bit++) {
 319                        if ((currByte & 0x01) ^ (crc & 0x01)) {
 320                                crc >>= 1;
 321                                crc = crc ^ 0xedb88320;
 322                        } else {
 323                                crc >>= 1;
 324                        }
 325                        currByte >>= 1;
 326                }
 327        }
 328
 329        crc = crc >> 26;
 330
 331        /* Set individual hash table register */
 332        if (crc >= 32) {
 333                fecp->ialr = (1 << (crc - 32));
 334                fecp->iaur = 0;
 335        } else {
 336                fecp->ialr = 0;
 337                fecp->iaur = (1 << crc);
 338        }
 339
 340        /* Set physical address */
 341        fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
 342        fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
 343
 344        /* Clear multicast address hash table */
 345        fecp->gaur = 0;
 346        fecp->galr = 0;
 347}
 348
 349static int fec_init(struct eth_device *dev, bd_t * bd)
 350{
 351        struct fec_info_dma *info = dev->priv;
 352        volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
 353        int i;
 354        uchar enetaddr[6];
 355
 356#ifdef ET_DEBUG
 357        printf("fec_init: iobase 0x%08x ...\n", info->iobase);
 358#endif
 359
 360        fecpin_setclear(dev, 1);
 361
 362        fec_halt(dev);
 363
 364#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
 365        defined (CONFIG_SYS_DISCOVER_PHY)
 366
 367        mii_init();
 368
 369        set_fec_duplex_speed(fecp, bd, info->dup_spd);
 370#else
 371#ifndef CONFIG_SYS_DISCOVER_PHY
 372        set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
 373#endif                          /* ifndef CONFIG_SYS_DISCOVER_PHY */
 374#endif                          /* CONFIG_CMD_MII || CONFIG_MII */
 375
 376        /* We use strictly polling mode only */
 377        fecp->eimr = 0;
 378
 379        /* Clear any pending interrupt */
 380        fecp->eir = 0xffffffff;
 381
 382        /* Set station address   */
 383        if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
 384                eth_env_get_enetaddr("ethaddr", enetaddr);
 385        else
 386                eth_env_get_enetaddr("eth1addr", enetaddr);
 387        fec_set_hwaddr(fecp, enetaddr);
 388
 389        /* Set Opcode/Pause Duration Register */
 390        fecp->opd = 0x00010020;
 391
 392        /* Setup Buffers and Buffer Descriptors */
 393        info->rxIdx = 0;
 394        info->txIdx = 0;
 395
 396        /* Setup Receiver Buffer Descriptors (13.14.24.18)
 397         * Settings:     Empty, Wrap */
 398        for (i = 0; i < PKTBUFSRX; i++) {
 399                info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 400                info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
 401                info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 402        }
 403        info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 404
 405        /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 406         * Settings:    Last, Tx CRC */
 407        for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
 408                info->txbd[i].cbd_sc = 0;
 409                info->txbd[i].cbd_datlen = 0;
 410                info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
 411        }
 412        info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
 413
 414        info->usedTbdIdx = 0;
 415        info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
 416
 417        /* Set Rx FIFO alarm and granularity value */
 418        fecp->rfcr = 0x0c000000;
 419        fecp->rfar = 0x0000030c;
 420
 421        /* Set Tx FIFO granularity value */
 422        fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
 423        fecp->tfar = 0x00000080;
 424
 425        fecp->tfwr = 0x2;
 426        fecp->ctcwr = 0x03000000;
 427
 428        /* Enable DMA receive task */
 429        MCD_startDma(info->rxTask,      /* Dma channel */
 430                     (s8 *) info->rxbd, /*Source Address */
 431                     0,         /* Source increment */
 432                     (s8 *) (&fecp->rfdr),      /* dest */
 433                     4,         /* dest increment */
 434                     0,         /* DMA size */
 435                     4,         /* xfer size */
 436                     info->rxInit,      /* initiator */
 437                     info->rxPri,       /* priority */
 438                     (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),        /* Flags */
 439                     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)   /* Function description */
 440            );
 441
 442        /* Enable DMA tx task with no ready buffer descriptors */
 443        MCD_startDma(info->txTask,      /* Dma channel */
 444                     (s8 *) info->txbd, /*Source Address */
 445                     0,         /* Source increment */
 446                     (s8 *) (&fecp->tfdr),      /* dest */
 447                     4,         /* dest incr */
 448                     0,         /* DMA size */
 449                     4,         /* xfer size */
 450                     info->txInit,      /* initiator */
 451                     info->txPri,       /* priority */
 452                     (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),        /* Flags */
 453                     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)   /* Function description */
 454            );
 455
 456        /* Now enable the transmit and receive processing */
 457        fecp->ecr |= FEC_ECR_ETHER_EN;
 458
 459        return 1;
 460}
 461
 462static void fec_halt(struct eth_device *dev)
 463{
 464        struct fec_info_dma *info = dev->priv;
 465        volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
 466        int counter = 0xffff;
 467
 468        /* issue graceful stop command to the FEC transmitter if necessary */
 469        fecp->tcr |= FEC_TCR_GTS;
 470
 471        /* wait for graceful stop to register */
 472        while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
 473
 474        /* Disable DMA tasks */
 475        MCD_killDma(info->txTask);
 476        MCD_killDma(info->rxTask);
 477
 478        /* Disable the Ethernet Controller */
 479        fecp->ecr &= ~FEC_ECR_ETHER_EN;
 480
 481        /* Clear FIFO status registers */
 482        fecp->rfsr &= FIFO_ERRSTAT;
 483        fecp->tfsr &= FIFO_ERRSTAT;
 484
 485        fecp->frst = 0x01000000;
 486
 487        /* Issue a reset command to the FEC chip */
 488        fecp->ecr |= FEC_ECR_RESET;
 489
 490        /* wait at least 20 clock cycles */
 491        udelay(10000);
 492
 493#ifdef ET_DEBUG
 494        printf("Ethernet task stopped\n");
 495#endif
 496}
 497
 498int mcdmafec_initialize(bd_t * bis)
 499{
 500        struct eth_device *dev;
 501        int i;
 502#ifdef CONFIG_SYS_DMA_USE_INTSRAM
 503        u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
 504#endif
 505
 506        for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
 507
 508                dev =
 509                    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
 510                                                  sizeof *dev);
 511                if (dev == NULL)
 512                        hang();
 513
 514                memset(dev, 0, sizeof(*dev));
 515
 516                sprintf(dev->name, "FEC%d", fec_info[i].index);
 517
 518                dev->priv = &fec_info[i];
 519                dev->init = fec_init;
 520                dev->halt = fec_halt;
 521                dev->send = fec_send;
 522                dev->recv = fec_recv;
 523
 524                /* setup Receive and Transmit buffer descriptor */
 525#ifdef CONFIG_SYS_DMA_USE_INTSRAM
 526                fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
 527                tmp = (u32)fec_info[i].rxbd;
 528                fec_info[i].txbd =
 529                    (cbd_t *)((u32)fec_info[i].txbd + tmp +
 530                    (PKTBUFSRX * sizeof(cbd_t)));
 531                tmp = (u32)fec_info[i].txbd;
 532                fec_info[i].txbuf =
 533                    (char *)((u32)fec_info[i].txbuf + tmp +
 534                    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 535                tmp = (u32)fec_info[i].txbuf;
 536#else
 537                fec_info[i].rxbd =
 538                    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
 539                                       (PKTBUFSRX * sizeof(cbd_t)));
 540                fec_info[i].txbd =
 541                    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
 542                                       (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 543                fec_info[i].txbuf =
 544                    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
 545#endif
 546
 547#ifdef ET_DEBUG
 548                printf("rxbd %x txbd %x\n",
 549                       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
 550#endif
 551
 552                fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
 553
 554                eth_register(dev);
 555
 556#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 557                int retval;
 558                struct mii_dev *mdiodev = mdio_alloc();
 559                if (!mdiodev)
 560                        return -ENOMEM;
 561                strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 562                mdiodev->read = mcffec_miiphy_read;
 563                mdiodev->write = mcffec_miiphy_write;
 564
 565                retval = mdio_register(mdiodev);
 566                if (retval < 0)
 567                        return retval;
 568#endif
 569
 570                if (i > 0)
 571                        fec_info[i - 1].next = &fec_info[i];
 572        }
 573        fec_info[i - 1].next = &fec_info[0];
 574
 575        /* default speed */
 576        bis->bi_ethspeed = 10;
 577
 578        return 0;
 579}
 580